mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
b3aaa87cba
Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal.
79 lines
2.1 KiB
Python
Executable File
79 lines
2.1 KiB
Python
Executable File
#!/usr/bin/python3
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import sys
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def usage():
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print("Usage: ./probes list_of_probes outfile")
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def header():
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return """create_debug_core u_ila_0 ila
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set_property C_DATA_DEPTH 16384 [get_debug_cores u_ila_0]
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set_property C_TRIGIN_EN false [get_debug_cores u_ila_0]
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set_property C_TRIGOUT_EN false [get_debug_cores u_ila_0]
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set_property C_ADV_TRIGGER false [get_debug_cores u_ila_0]
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set_property C_INPUT_PIPE_STAGES 0 [get_debug_cores u_ila_0]
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set_property C_EN_STRG_QUAL false [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0]
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set_property ALL_PROBE_SAME_MU_CNT 1 [get_debug_cores u_ila_0]
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startgroup
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set_property C_EN_STRG_QUAL true [get_debug_cores u_ila_0 ]
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set_property C_ADV_TRIGGER true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU true [get_debug_cores u_ila_0 ]
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set_property ALL_PROBE_SAME_MU_CNT 4 [get_debug_cores u_ila_0 ]
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endgroup
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connect_debug_port u_ila_0/clk [get_nets [list xlnx_ddr4_c0/inst/u_ddr4_infrastructure/addn_ui_clkout1 ]]"""
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def convertLine(x):
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temp = x.split()
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temp[1] = int(temp[1])
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temp[2] = int(temp[2])
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return tuple(temp)
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def probeBits( probe ):
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str = ''
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if (probe[1] > 1):
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for i in range(probe[1]):
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if i != (probe[1]-1):
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str = str + f"{{{probe[0]}[{i}]}} "
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else:
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str = str + f"{{{probe[0]}[{i}]}} "
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else:
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str = f'{{{probe[0]}}}'
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return str
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def printProbe( probe,):
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bits = probeBits(probe)
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return (
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f'create_debug_port u_ila_0 probe\n'
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f'set_property port_width {probe[1]} [get_debug_ports u_ila_0/probe{probe[2]}]\n'
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f'set_property PROBE_TYPE DATA_AND_TRIGGER [get_debug_ports u_ila_0/probe{probe[2]}]\n'
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f'connect_debug_port u_ila_0/probe{probe[2]} [get_nets [list {bits}]]\n\n'
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)
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def main(args):
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if (len(args) != 2):
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usage()
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exit()
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probeList = []
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with open(args[0]) as probeListFile:
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probeList = list(map(convertLine, probeListFile.readlines()))
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with open(args[1], 'w') as outfile:
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# outfile.write(header())
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# outfile.write("\n\n")
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for i in range(len(probeList)):
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outfile.write(printProbe(probeList[i]))
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if __name__ == '__main__':
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main(sys.argv[1:])
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