mirror of
https://github.com/openhwgroup/cvw
synced 2025-01-23 21:14:37 +00:00
51 lines
1.5 KiB
ArmAsm
51 lines
1.5 KiB
ArmAsm
##########################################
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# dcache2.S
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#
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# Written: avercruysse@hmc.edu 18 April 2023
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#
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# Purpose: Test Coverage for D$
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# (for all 4 cache ways, trigger a FlushStage while SetDirtyWay=1)
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#
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# A component of the CORE-V-WALLY configurable RISC-V project.
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# https://github.com/openhwgroup/cvw
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#
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# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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#
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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# except in compliance with the License, or, at your option, the Apache License version 2.0. You
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# may obtain a copy of the License at
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#
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# https://solderpad.org/licenses/SHL-2.1/
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#
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# Unless required by applicable law or agreed to in writing, any work distributed under the
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# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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# either express or implied. See the License for the specific language governing permissions
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# and limitations under the License.
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##############################################################################################
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#include "WALLY-init-lib.h"
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main:
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# way 0
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li t0, 0x80100770
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sd zero, 0(t0)
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sd zero, 1(t0)
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# way 1
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li t0, 0x80101770
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sd zero, 0(t0)
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sd zero, 1(t0)
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# way 2
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li t0, 0x80102770
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sd zero, 0(t0)
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sd zero, 1(t0)
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# way 3
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li t0, 0x80103770
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sd zero, 0(t0)
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sd zero, 1(t0)
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j done
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