David Harris ffc2a2097a Removed unnecessary generate inside hptw		2021-12-30 21:21:00 +00:00
..
adrdec.sv	Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.	2021-06-24 19:59:29 -04:00
adrdecs.sv	Renamed dtim->ram and boottim ->bootrom	2021-12-14 13:43:06 -08:00
decoder.sv	remove redundant decodes, fixed mmu logic ins/outs	2021-06-07 19:23:30 -04:00
hptw.sv	Removed unnecessary generate inside hptw	2021-12-30 21:21:00 +00:00
mmu.sv	Added names to generate blocks	2021-12-30 20:55:48 +00:00
pmachecker.sv	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
pmpadrdec.sv	removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.	2021-10-08 15:33:18 -07:00
pmpchecker.sv	Added wally-riscv-arch-test MMU tests and removed imperas MMU tests from regresssion	2021-12-30 17:22:18 +00:00
priorityonehot.sv	IEU cleanup	2021-10-23 11:13:28 -07:00
prioritythermometer.sv	IEU cleanup	2021-10-23 11:13:28 -07:00
tlb.sv	Removed the fault state from the hptw. Now writing TLB faults into the I/DTLBs. This has two advantages.	2021-12-23 12:40:22 -06:00
tlbcam.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbcamline.sv	Added names to generate blocks	2021-12-30 20:55:48 +00:00
tlbcontrol.sv	Added names to generate blocks	2021-12-30 20:55:48 +00:00
tlblru.sv	Cleaned up priority thermometer verilog. passses regression, ideally shortens critical path through pmp's	2021-07-23 11:57:58 -05:00
tlbmixer.sv	Broken.	2021-07-19 10:33:27 -05:00
tlbram.sv	Replaced .or with or_rows structural code in MMU read circuitry for synthesis.	2021-07-13 09:32:02 -04:00
tlbramline.sv	fixed issues with dc shell not liking modules with parameters without default values.	2021-10-18 17:24:15 -05:00