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https://github.com/openhwgroup/cvw
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315 lines
11 KiB
Systemverilog
315 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// wallypipelinedhart.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Pipelined RISC-V Processor
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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/* verilator lint_on UNUSED */
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module wallypipelinedhart
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(
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input logic clk, reset,
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output logic [`XLEN-1:0] PCF,
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// input logic [31:0] InstrF,
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// Privileged
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input logic TimerIntM, ExtIntM, SwIntM,
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input logic DataAccessFaultM,
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input logic [63:0] MTIME_CLINT, MTIMECMP_CLINT,
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// Bus Interface
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input logic [15:0] rd2, // bogus, delete when real multicycle fetch works
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input logic [`AHBW-1:0] HRDATA,
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input logic HREADY, HRESP,
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output logic HCLK, HRESETn,
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output logic [31:0] HADDR,
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output logic [`AHBW-1:0] HWDATA,
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output logic HWRITE,
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output logic [2:0] HSIZE,
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output logic [2:0] HBURST,
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output logic [3:0] HPROT,
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output logic [1:0] HTRANS,
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output logic HMASTLOCK,
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output logic [5:0] HSELRegions,
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// Delayed signals for subword write
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output logic [2:0] HADDRD,
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output logic [3:0] HSIZED,
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output logic HWRITED
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);
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// logic [1:0] ForwardAE, ForwardBE;
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logic StallF, StallD, StallE, StallM, StallW;
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logic FlushF, FlushD, FlushE, FlushM, FlushW;
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logic RetM;
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(* mark_debug = "true" *) logic TrapM;
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// new signals that must connect through DP
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logic MulDivE, W64E;
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logic CSRReadM, CSRWriteM, PrivilegedM;
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logic [1:0] AtomicE;
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logic [1:0] AtomicM;
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logic [`XLEN-1:0] SrcAE, SrcBE;
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logic [`XLEN-1:0] SrcAM;
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logic [2:0] Funct3E;
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// logic [31:0] InstrF;
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logic [31:0] InstrD, InstrE, InstrW;
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(* mark_debug = "true" *) logic [31:0] InstrM;
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logic [`XLEN-1:0] PCD, PCE, PCLinkE, PCLinkW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] PCM;
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logic [`XLEN-1:0] PCTargetE;
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logic [`XLEN-1:0] CSRReadValW, MulDivResultW;
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logic [`XLEN-1:0] PrivilegedNextPCM;
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logic [1:0] MemRWE;
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(* mark_debug = "true" *) logic [1:0] MemRWM;
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(* mark_debug = "true" *) logic InstrValidM;
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logic InstrMisalignedFaultM;
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logic DataMisalignedM;
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logic IllegalBaseInstrFaultD, IllegalIEUInstrFaultD;
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logic ITLBInstrPageFaultF, DTLBLoadPageFaultM, DTLBStorePageFaultM;
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logic WalkerInstrPageFaultF, WalkerLoadPageFaultM, WalkerStorePageFaultM;
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logic LoadMisalignedFaultM, LoadAccessFaultM;
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logic StoreMisalignedFaultM, StoreAccessFaultM;
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logic [`XLEN-1:0] InstrMisalignedAdrM;
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logic InvalidateICacheM, FlushDCacheM;
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logic PCSrcE;
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logic CSRWritePendingDEM;
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logic DivBusyE;
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logic RegWriteD;
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logic LoadStallD, StoreStallD, MulDivStallD, CSRRdStallD;
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logic SquashSCM, SquashSCW;
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// floating point unit signals
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logic [2:0] FRM_REGW;
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logic [1:0] FMemRWM, FMemRWE;
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logic [4:0] RdE, RdM, RdW;
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logic FStallD;
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logic FWriteIntE, FWriteIntM, FWriteIntW;
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logic [`XLEN-1:0] FWriteDataE;
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logic [`XLEN-1:0] FIntResM;
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logic FDivBusyE;
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logic IllegalFPUInstrD, IllegalFPUInstrE;
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logic FRegWriteM;
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logic FPUStallD;
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logic [4:0] SetFflagsM;
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logic [`XLEN-1:0] FPUResultW;
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// memory management unit signals
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logic ITLBWriteF, DTLBWriteM;
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logic ITLBFlushF, DTLBFlushM;
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logic ITLBMissF, ITLBHitF;
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logic DTLBMissM, DTLBHitM;
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logic [`XLEN-1:0] SATP_REGW;
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logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
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logic [1:0] STATUS_MPP;
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logic [1:0] PrivilegeModeW;
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logic [`XLEN-1:0] PTE;
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logic [1:0] PageType;
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// PMA checker signals
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logic DSquashBusAccessM, ISquashBusAccessF;
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var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
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var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
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// IMem stalls
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logic ICacheStallF;
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logic LSUStall;
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// cpu lsu interface
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logic [2:0] Funct3M;
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logic [`XLEN-1:0] MemAdrE;
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(* mark_debug = "true" *) logic [`XLEN-1:0] WriteDataM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MemAdrM;
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(* mark_debug = "true" *) logic [`XLEN-1:0] ReadDataM;
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logic [`XLEN-1:0] ReadDataW;
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logic CommittedM;
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// AHB ifu interface
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logic [`PA_BITS-1:0] InstrPAdrF;
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logic [`XLEN-1:0] InstrRData;
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logic InstrReadF;
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logic InstrAckF;
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// AHB LSU interface
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logic [`PA_BITS-1:0] DCtoAHBPAdrM;
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logic DCtoAHBReadM;
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logic DCtoAHBWriteM;
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logic DCfromAHBAck;
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logic [`XLEN-1:0] DCfromAHBReadData;
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logic [`XLEN-1:0] DCtoAHBWriteData;
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logic BPPredWrongE;
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logic BPPredDirWrongM;
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logic BTBPredPCWrongM;
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logic RASPredPCWrongM;
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logic BPPredClassNonCFIWrongM;
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logic [4:0] InstrClassM;
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logic InstrAccessFaultF;
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logic [2:0] DCtoAHBSizeM;
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logic ExceptionM;
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logic PendingInterruptM;
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logic DCacheMiss;
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logic DCacheAccess;
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logic BreakpointFaultM, EcallFaultM;
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ifu ifu(.InstrInF(InstrRData),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.*); // instruction fetch unit: PC, branch prediction, instruction cache
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ieu ieu(.*); // integer execution unit: integer register file, datapath and controller
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lsu lsu(.clk(clk),
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.reset(reset),
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.StallM(StallM),
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.FlushM(FlushM),
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.StallW(StallW),
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.FlushW(FlushW),
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// CPU interface
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.MemRWM(MemRWM),
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.Funct3M(Funct3M),
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.Funct7M(InstrM[31:25]),
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.AtomicM(AtomicM),
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.ExceptionM(ExceptionM),
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.PendingInterruptM(PendingInterruptM),
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.CommittedM(CommittedM),
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.DCacheMiss,
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.DCacheAccess,
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.SquashSCW(SquashSCW),
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.DataMisalignedM(DataMisalignedM),
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.MemAdrE(MemAdrE),
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.MemAdrM(MemAdrM),
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.WriteDataM(WriteDataM),
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.ReadDataM(ReadDataM),
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.FlushDCacheM,
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// connected to ahb (all stay the same)
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.DCtoAHBPAdrM(DCtoAHBPAdrM),
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.DCtoAHBReadM(DCtoAHBReadM),
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.DCtoAHBWriteM(DCtoAHBWriteM),
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.DCfromAHBAck(DCfromAHBAck),
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.DCfromAHBReadData(DCfromAHBReadData),
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.DCtoAHBWriteData(DCtoAHBWriteData),
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.DCtoAHBSizeM(DCtoAHBSizeM),
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// connect to csr or privilege and stay the same.
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.PrivilegeModeW(PrivilegeModeW), // connects to csr
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.PMPCFG_ARRAY_REGW(PMPCFG_ARRAY_REGW), // connects to csr
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.PMPADDR_ARRAY_REGW(PMPADDR_ARRAY_REGW), // connects to csr
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// hptw keep i/o
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.SATP_REGW(SATP_REGW), // from csr
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.STATUS_MXR(STATUS_MXR), // from csr
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.STATUS_SUM(STATUS_SUM), // from csr
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.STATUS_MPRV(STATUS_MPRV), // from csr
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.STATUS_MPP(STATUS_MPP), // from csr
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.DTLBFlushM(DTLBFlushM), // connects to privilege
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.DTLBLoadPageFaultM(DTLBLoadPageFaultM), // connects to privilege
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.DTLBStorePageFaultM(DTLBStorePageFaultM), // connects to privilege
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.LoadMisalignedFaultM(LoadMisalignedFaultM), // connects to privilege
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.LoadAccessFaultM(LoadAccessFaultM), // connects to privilege
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.StoreMisalignedFaultM(StoreMisalignedFaultM), // connects to privilege
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.StoreAccessFaultM(StoreAccessFaultM), // connects to privilege
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.PCF(PCF),
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.ITLBMissF(ITLBMissF),
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.PTE(PTE),
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.PageType,
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.ITLBWriteF(ITLBWriteF),
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.WalkerInstrPageFaultF(WalkerInstrPageFaultF),
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.WalkerLoadPageFaultM(WalkerLoadPageFaultM),
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.WalkerStorePageFaultM(WalkerStorePageFaultM),
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.DTLBHitM(DTLBHitM), // not connected remove
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.LSUStall(LSUStall)); // change to LSUStall
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ahblite ebu(// IFU connections
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.InstrPAdrF(InstrPAdrF),
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.InstrReadF(InstrReadF),
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.InstrRData(InstrRData),
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.InstrAckF(InstrAckF),
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// LSU connections
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.DCtoAHBPAdrM(DCtoAHBPAdrM), // rename to DCtoAHBPAdrM
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.DCtoAHBReadM(DCtoAHBReadM), // rename to DCtoAHBReadM
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.DCtoAHBWriteM(DCtoAHBWriteM), // rename to DCtoAHBWriteM
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.DCtoAHBWriteData(DCtoAHBWriteData),
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.DCfromAHBReadData(DCfromAHBReadData),
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.DCfromAHBAck(DCfromAHBAck),
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// remove these
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.MemSizeM(DCtoAHBSizeM[1:0]), // *** depends on XLEN should be removed
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.UnsignedLoadM(1'b0),
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.Funct7M(7'b0),
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// .HRDATAW(),
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.StallW(1'b0),
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.AtomicMaskedM(2'b00),
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.*);
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muldiv mdu(.*); // multiply and divide unit
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hazard hzu(.*); // global stall and flush control
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// Priveleged block operates in M and W stages, handling CSRs and exceptions
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privileged priv(.*);
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fpu fpu(.*); // floating point unit
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// add FPU here, with SetFflagsM, FRM_REGW
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// presently stub out SetFlagsM and FRegWriteM
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//assign SetFflagsM = 0;
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//assign FRegWriteM = 0;
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/* -----\/----- EXCLUDED -----\/-----
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// ILA probe most important signals in CPU.
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ila_0 ila_0(.clk(clk),
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.probe0(PCM),
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.probe1(MemAdrM),
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.probe2(WriteDataM),
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.probe3(ReadDataM),
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.probe4(TrapM),
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.probe5(MemRWM),
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.probe6(InstrM),
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.probe7(InstrValidM),
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.probe8({PendingIntsM, InstrMisalignedFaultM , InstrAccessFaultM , IllegalInstrFaultM ,
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LoadMisalignedFaultM , StoreMisalignedFaultM ,
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InstrPageFaultM , LoadPageFaultM , StorePageFaultM ,
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BreakpointFaultM , EcallFaultM ,
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LoadAccessFaultM , StoreAccessFaultM}),
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.probe9(MEPC_REGW),
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.probe10(MCAUSE_REGW),
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.probe11(MTVAL_REGW),
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.probe12(MIP_REGW),
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.probe13(MIE_REGW),
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.probe14(SIP_REGW),
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.probe15(SIE_REGW),
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.probe16({Match, SizeValid, Supported, AccessValid}));
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-----/\----- EXCLUDED -----/\----- */
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endmodule
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