mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
119 lines
2.6 KiB
Plaintext
119 lines
2.6 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "wally-virt";
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model = "wally-virt,qemu";
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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bootargs = "root=/dev/vda ro console=ttyS0,115200 loglevel=7";
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stdout-path = "/soc/uart@10000000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x80000000>;
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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clock-frequency = <0x2FAF080>;
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timebase-frequency = <0x2FAF080>;
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cpu@0 {
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phandle = <0x01>;
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device_type = "cpu";
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-base = "rv64i";
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riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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riscv,cbom-block-size = <64>;
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x02>;
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};
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};
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};
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soc {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "simple-bus";
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ranges;
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refclk: refclk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0x2FAF080>;
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clock-output-names = "xtal";
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};
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gpio0: gpio@10060000 {
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compatible = "sifive,gpio0";
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interrupt-parent = <0x03>;
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interrupts = <3>;
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reg = <0x00 0x10060000 0x00 0x1000>;
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reg-names = "control";
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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uart@10000000 {
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interrupts = <0x0a>;
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interrupt-parent = <0x03>;
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clock-frequency = <0x2FAF080>;
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reg = <0x00 0x10000000 0x00 0x100>;
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compatible = "ns16550a";
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};
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plic@c000000 {
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phandle = <0x03>;
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riscv,ndev = <0x35>;
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reg = <0x00 0xc000000 0x00 0x210000>;
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interrupts-extended = <0x02 0x0b 0x02 0x09>;
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interrupt-controller;
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compatible = "sifive,plic-1.0.0\0riscv,plic0";
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#interrupt-cells = <0x01>;
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#address-cells = <0x00>;
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};
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spi@13000 {
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compatible = "sifive,spi0";
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interrupt-parent = <0x03>;
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interrupts = <0x14>;
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reg = <0x0 0x13000 0x0 0x1000>;
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reg-names = "control";
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clocks = <&refclk>;
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#address-cells = <1>;
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#size-cells = <0>;
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mmc@0 {
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compatible = "mmc-spi-slot";
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reg = <0>;
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spi-max-frequency = <1000000>;
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voltage-ranges = <3300 3300>;
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disable-wp;
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// gpios = <&gpio0 6 1>;
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};
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};
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clint@2000000 {
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interrupts-extended = <0x02 0x03 0x02 0x07>;
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reg = <0x00 0x2000000 0x00 0x10000>;
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compatible = "sifive,clint0\0riscv,clint0";
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};
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};
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};
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