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194 lines
10 KiB
Systemverilog
194 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// crsr.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Status register
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// See RISC-V Privileged Mode Specification 20190608
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csrsr (
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input logic clk, reset, StallW,
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input logic WriteMSTATUSM, WriteSSTATUSM, WriteUSTATUSM,
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input logic TrapM, FRegWriteM,
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input logic [1:0] NextPrivilegeModeM, PrivilegeModeW,
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input logic mretM, sretM, uretM,
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input logic WriteFRMM, WriteFFLAGSM,
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input logic [`XLEN-1:0] CSRWriteValM,
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output logic [`XLEN-1:0] MSTATUS_REGW, SSTATUS_REGW, USTATUS_REGW,
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output logic [1:0] STATUS_MPP,
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output logic STATUS_SPP, STATUS_TSR, STATUS_TW,
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output logic STATUS_MIE, STATUS_SIE,
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output logic STATUS_MXR, STATUS_SUM,
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output logic STATUS_MPRV, STATUS_TVM
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);
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logic STATUS_SD, STATUS_TW_INT, STATUS_TSR_INT, STATUS_TVM_INT, STATUS_MXR_INT, STATUS_SUM_INT, STATUS_MPRV_INT;
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logic [1:0] STATUS_SXL, STATUS_UXL, STATUS_XS, STATUS_FS, STATUS_FS_INT, STATUS_MPP_NEXT;
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logic STATUS_MPIE, STATUS_SPIE, STATUS_UPIE, STATUS_UIE;
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// STATUS REGISTER FIELD
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// See Privileged Spec Section 3.1.6
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// Lower privilege status registers are a subset of the full status register
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// *** consider adding MBE, SBE, UBE fields later from 20210108 draft spec
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if (`XLEN==64) begin: csrsr64 // RV64
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assign MSTATUS_REGW = {STATUS_SD, 27'b0, STATUS_SXL, STATUS_UXL, 9'b0,
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STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
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STATUS_SPP, STATUS_MPIE, 1'b0, STATUS_SPIE, STATUS_UPIE,
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STATUS_MIE, 1'b0, STATUS_SIE, STATUS_UIE};
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assign SSTATUS_REGW = {STATUS_SD, /*27'b0, */ 29'b0, /*STATUS_SXL, */ STATUS_UXL, /*9'b0, */ 12'b0,
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/*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
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STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
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STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE,
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/*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE};
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assign USTATUS_REGW = {/*STATUS_SD, */ 59'b0, /*STATUS_SXL, STATUS_UXL, 9'b0, */
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/*STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, , 1'b0,*/
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/* STATUS_XS, STATUS_FS, /*STATUS_MPP, 8'b0, */
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/*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE,
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/*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE};
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end else begin: csrsr32 // RV32
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assign MSTATUS_REGW = {STATUS_SD, 8'b0,
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STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV,
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STATUS_XS, STATUS_FS, STATUS_MPP, 2'b0,
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STATUS_SPP, STATUS_MPIE, 1'b0, STATUS_SPIE, STATUS_UPIE, STATUS_MIE, 1'b0, STATUS_SIE, STATUS_UIE};
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assign SSTATUS_REGW = {STATUS_SD, 11'b0,
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/*STATUS_TSR, STATUS_TW, STATUS_TVM, */STATUS_MXR, STATUS_SUM, /* STATUS_MPRV, */ 1'b0,
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STATUS_XS, STATUS_FS, /*STATUS_MPP, 2'b0*/ 4'b0,
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STATUS_SPP, /*STATUS_MPIE, 1'b0*/ 2'b0, STATUS_SPIE, STATUS_UPIE,
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/*STATUS_MIE, 1'b0*/ 2'b0, STATUS_SIE, STATUS_UIE};
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assign USTATUS_REGW = {/*STATUS_SD, */ 27'b0, /*STATUS_SXL, STATUS_UXL, 9'b0, */
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/*STATUS_TSR, STATUS_TW, STATUS_TVM, STATUS_MXR, STATUS_SUM, STATUS_MPRV, , 1'b0,*/
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/*STATUS_XS, STATUS_FS, STATUS_MPP, 8'b0, */
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/*STATUS_SPP, STATUS_MPIE, 1'b0 2'b0, STATUS_SPIE,*/ STATUS_UPIE,
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/*STATUS_MIE, 1'b0*/ 3'b0, /*STATUS_SIE, */STATUS_UIE};
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end
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// harwired STATUS bits
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assign STATUS_TSR = `S_SUPPORTED & STATUS_TSR_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_TW = (`S_SUPPORTED | `U_SUPPORTED) & STATUS_TW_INT; // override reigster with 0 if only machine mode supported
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assign STATUS_TVM = `S_SUPPORTED & STATUS_TVM_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_MXR = `S_SUPPORTED & STATUS_MXR_INT; // override reigster with 0 if supervisor mode not supported
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// SXL and UXL bits only matter for RV64. Set to 10 for RV64 if mode is supported, or 0 if not
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assign STATUS_SXL = `S_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if supervisor mode supported
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assign STATUS_UXL = `U_SUPPORTED & ~`QEMU ? 2'b10 : 2'b00; // 10 if user mode supported
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assign STATUS_SUM = `S_SUPPORTED & `VIRTMEM_SUPPORTED & STATUS_SUM_INT; // override reigster with 0 if supervisor mode not supported
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assign STATUS_MPRV = `U_SUPPORTED & STATUS_MPRV_INT; // override with 0 if user mode not supported
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assign STATUS_FS = (`S_SUPPORTED & (`F_SUPPORTED | `D_SUPPORTED)) ? STATUS_FS_INT : 2'b00; // off if no FP
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assign STATUS_SD = (STATUS_FS == 2'b11) | (STATUS_XS == 2'b11); // dirty state logic
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assign STATUS_XS = 2'b00; // No additional user-mode state to be dirty
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always_comb
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if (CSRWriteValM[12:11] == `U_MODE & `U_SUPPORTED) STATUS_MPP_NEXT = `U_MODE;
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else if (CSRWriteValM[12:11] == `S_MODE & `S_SUPPORTED) STATUS_MPP_NEXT = `S_MODE;
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else STATUS_MPP_NEXT = `M_MODE;
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// registers for STATUS bits
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// complex register with reset, write enable, and the ability to update other bits in certain cases
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always_ff @(posedge clk) //, posedge reset)
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if (reset) begin
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STATUS_TSR_INT <= #1 0;
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STATUS_TW_INT <= #1 0;
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STATUS_TVM_INT <= #1 0;
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STATUS_MXR_INT <= #1 0;
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STATUS_SUM_INT <= #1 0;
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STATUS_MPRV_INT <= #1 0; // Per Priv 3.3
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STATUS_FS_INT <= #1 0;
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STATUS_MPP <= #1 0; //`M_MODE;
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STATUS_SPP <= #1 0; //1'b1;
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STATUS_MPIE <= #1 0; //1;
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STATUS_SPIE <= #1 0; //`S_SUPPORTED;
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STATUS_UPIE <= #1 0; // `U_SUPPORTED;
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STATUS_MIE <= #1 0; // Per Priv 3.3
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STATUS_SIE <= #1 0; //`S_SUPPORTED;
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STATUS_UIE <= #1 0; //`U_SUPPORTED;
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end else if (~StallW) begin
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if (FRegWriteM | WriteFRMM | WriteFFLAGSM) STATUS_FS_INT <= #12'b11; // mark Float State dirty *** this should happen in M stage, be part of if/else;
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if (TrapM) begin
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// Update interrupt enables per Privileged Spec p. 21
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// y = PrivilegeModeW
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// x = NextPrivilegeModeM
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// Modes: 11 = Machine, 01 = Supervisor, 00 = User
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if (NextPrivilegeModeM == `M_MODE) begin
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STATUS_MPIE <= #1 STATUS_MIE;
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STATUS_MIE <= #1 0;
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STATUS_MPP <= #1 PrivilegeModeW;
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end else if (NextPrivilegeModeM == `S_MODE) begin
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STATUS_SPIE <= #1 STATUS_SIE;
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STATUS_SIE <= #1 0;
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STATUS_SPP <= #1 PrivilegeModeW[0]; // *** seems to disagree with P. 56
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end else begin // user mode
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STATUS_UPIE <= #1 STATUS_UIE;
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STATUS_UIE <= #1 0;
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end
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end else if (mretM) begin // Privileged 3.1.6.1
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STATUS_MIE <= #1 STATUS_MPIE;
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STATUS_MPIE <= #1 1;
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STATUS_MPP <= #1 `U_SUPPORTED ? `U_MODE : `M_MODE; // per spec, not sure why
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STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec
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end else if (sretM) begin
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STATUS_SIE <= #1 STATUS_SPIE;
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STATUS_SPIE <= #1 `S_SUPPORTED;
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STATUS_SPP <= #1 0; // Privileged 4.1.1
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STATUS_MPRV_INT <= #1 0; // per 20210108 draft spec
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end else if (uretM) begin
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STATUS_UIE <= #1 STATUS_UPIE;
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STATUS_UPIE <= #1 `U_SUPPORTED;
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end else if (WriteMSTATUSM) begin
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STATUS_TSR_INT <= #1 CSRWriteValM[22];
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STATUS_TW_INT <= #1 CSRWriteValM[21];
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STATUS_TVM_INT <= #1 CSRWriteValM[20];
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STATUS_MXR_INT <= #1 CSRWriteValM[19];
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STATUS_SUM_INT <= #1 CSRWriteValM[18];
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STATUS_MPRV_INT <= #1 CSRWriteValM[17];
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STATUS_FS_INT <= #1 CSRWriteValM[14:13];
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STATUS_MPP <= #1 STATUS_MPP_NEXT;
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STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
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STATUS_MPIE <= #1 CSRWriteValM[7];
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STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
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STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4];
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STATUS_MIE <= #1 CSRWriteValM[3];
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STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
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STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0];
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end else if (WriteSSTATUSM) begin // write a subset of the STATUS bits
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STATUS_MXR_INT <= #1 CSRWriteValM[19];
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STATUS_SUM_INT <= #1 CSRWriteValM[18];
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STATUS_FS_INT <= #1 CSRWriteValM[14:13];
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STATUS_SPP <= #1 `S_SUPPORTED & CSRWriteValM[8];
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STATUS_SPIE <= #1 `S_SUPPORTED & CSRWriteValM[5];
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STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4];
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STATUS_SIE <= #1 `S_SUPPORTED & CSRWriteValM[1];
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STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0];
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end else if (WriteUSTATUSM) begin // write a subset of the STATUS bits
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STATUS_FS_INT <= #1 CSRWriteValM[14:13];
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STATUS_UPIE <= #1 `U_SUPPORTED & CSRWriteValM[4];
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STATUS_UIE <= #1 `U_SUPPORTED & CSRWriteValM[0];
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end
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end
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endmodule
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