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210 lines
10 KiB
Systemverilog
210 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// csrm.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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// dottolia@hmc.edu 7 April 2021
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//
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// Purpose: Machine-Mode Control and Status Registers
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// See RISC-V Privileged Mode Specification 20190608
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csrm #(parameter
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// Machine CSRs
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MVENDORID = 12'hF11,
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MARCHID = 12'hF12,
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MIMPID = 12'hF13,
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MHARTID = 12'hF14,
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MSTATUS = 12'h300,
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MISA_ADR = 12'h301,
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MEDELEG = 12'h302,
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MIDELEG = 12'h303,
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MIE = 12'h304,
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MTVEC = 12'h305,
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MCOUNTEREN = 12'h306,
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MSTATUSH = 12'h310,
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MCOUNTINHIBIT = 12'h320,
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MSCRATCH = 12'h340,
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MEPC = 12'h341,
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MCAUSE = 12'h342,
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MTVAL = 12'h343,
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MIP = 12'h344,
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PMPCFG0 = 12'h3A0,
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// .. up to 15 more at consecutive addresses
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PMPADDR0 = 12'h3B0,
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// ... up to 63 more at consecutive addresses
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TSELECT = 12'h7A0,
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TDATA1 = 12'h7A1,
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TDATA2 = 12'h7A2,
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TDATA3 = 12'h7A3,
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DCSR = 12'h7B0,
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DPC = 12'h7B1,
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DSCRATCH0 = 12'h7B2,
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DSCRATCH1 = 12'h7B3,
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// Constants
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ZERO = {(`XLEN){1'b0}},
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MEDELEG_MASK = ~(ZERO | `XLEN'b1 << 11),
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MIDELEG_MASK = {{(`XLEN-12){1'b0}}, 12'h222}
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) (
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input logic clk, reset,
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input logic InstrValidNotFlushedM, StallW,
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input logic CSRMWriteM, MTrapM,
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input logic [11:0] CSRAdrM,
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input logic [`XLEN-1:0] NextEPCM, NextCauseM, NextMtvalM, MSTATUS_REGW,
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input logic [`XLEN-1:0] CSRWriteValM,
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output logic [`XLEN-1:0] CSRMReadValM, MTVEC_REGW,
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(* mark_debug = "true" *) output logic [`XLEN-1:0] MEPC_REGW,
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output logic [31:0] MCOUNTEREN_REGW, MCOUNTINHIBIT_REGW,
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output logic [`XLEN-1:0] MEDELEG_REGW, MIDELEG_REGW,
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// 64-bit registers in RV64, or two 32-bit registers in RV32
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//output var logic [63:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES/8-1:0],
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output var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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output var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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(* mark_debug = "true" *) input logic [11:0] MIP_REGW, MIE_REGW,
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output logic WriteMSTATUSM,
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output logic IllegalCSRMAccessM, IllegalCSRMWriteReadonlyM
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);
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logic [`XLEN-1:0] MISA_REGW, MHARTID_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MSCRATCH_REGW;
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(* mark_debug = "true" *) logic [`XLEN-1:0] MCAUSE_REGW, MTVAL_REGW;
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logic WriteMTVECM, WriteMEDELEGM, WriteMIDELEGM;
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logic WriteMSCRATCHM, WriteMEPCM, WriteMCAUSEM, WriteMTVALM;
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logic WriteMCOUNTERENM, WriteMCOUNTINHIBITM;
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// There are PMP_ENTRIES = 0, 16, or 64 PMPADDR registers, each of which has its own flop
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genvar i;
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if (`PMP_ENTRIES > 0) begin:pmp
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logic [`PMP_ENTRIES-1:0] WritePMPCFGM;
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logic [`PMP_ENTRIES-1:0] WritePMPADDRM ;
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logic [`PMP_ENTRIES-1:0] ADDRLocked, CFGLocked;
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for(i=0; i<`PMP_ENTRIES; i++) begin
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// when the lock bit is set, don't allow writes to the PMPCFG or PMPADDR
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// also, when the lock bit of the next entry is set and the next entry is TOR, don't allow writes to this entry PMPADDR
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assign CFGLocked[i] = PMPCFG_ARRAY_REGW[i][7];
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if (i == `PMP_ENTRIES-1)
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assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7];
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else
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assign ADDRLocked[i] = PMPCFG_ARRAY_REGW[i][7] | (PMPCFG_ARRAY_REGW[i+1][7] & PMPCFG_ARRAY_REGW[i+1][4:3] == 2'b01);
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assign WritePMPADDRM[i] = (CSRMWriteM & (CSRAdrM == (PMPADDR0+i))) & InstrValidNotFlushedM & ~ADDRLocked[i];
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flopenr #(`XLEN) PMPADDRreg(clk, reset, WritePMPADDRM[i], CSRWriteValM, PMPADDR_ARRAY_REGW[i]);
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if (`XLEN==64) begin
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+2*(i/8)))) & InstrValidNotFlushedM & ~CFGLocked[i];
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%8)*8+7:(i%8)*8], PMPCFG_ARRAY_REGW[i]);
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end else begin
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assign WritePMPCFGM[i] = (CSRMWriteM & (CSRAdrM == (PMPCFG0+i/4))) & InstrValidNotFlushedM & ~CFGLocked[i];
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flopenr #(8) PMPCFGreg(clk, reset, WritePMPCFGM[i], CSRWriteValM[(i%4)*8+7:(i%4)*8], PMPCFG_ARRAY_REGW[i]);
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end
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end
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end
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localparam MISA_26 = (`MISA) & 32'h03ffffff;
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// MISA is hardwired. Spec says it could be written to disable features, but this is not supported by Wally
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assign MISA_REGW = {(`XLEN == 32 ? 2'b01 : 2'b10), {(`XLEN-28){1'b0}}, MISA_26[25:0]};
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// MHARTID is hardwired. It only exists as a signal so that the testbench can easily see it.
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assign MHARTID_REGW = 0;
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// Write machine Mode CSRs
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assign WriteMSTATUSM = CSRMWriteM & (CSRAdrM == MSTATUS) & InstrValidNotFlushedM;
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assign WriteMTVECM = CSRMWriteM & (CSRAdrM == MTVEC) & InstrValidNotFlushedM;
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assign WriteMEDELEGM = CSRMWriteM & (CSRAdrM == MEDELEG) & InstrValidNotFlushedM;
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assign WriteMIDELEGM = CSRMWriteM & (CSRAdrM == MIDELEG) & InstrValidNotFlushedM;
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assign WriteMSCRATCHM = CSRMWriteM & (CSRAdrM == MSCRATCH) & InstrValidNotFlushedM;
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assign WriteMEPCM = MTrapM | (CSRMWriteM & (CSRAdrM == MEPC)) & InstrValidNotFlushedM;
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assign WriteMCAUSEM = MTrapM | (CSRMWriteM & (CSRAdrM == MCAUSE)) & InstrValidNotFlushedM;
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assign WriteMTVALM = MTrapM | (CSRMWriteM & (CSRAdrM == MTVAL)) & InstrValidNotFlushedM;
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assign WriteMCOUNTERENM = CSRMWriteM & (CSRAdrM == MCOUNTEREN) & InstrValidNotFlushedM;
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assign WriteMCOUNTINHIBITM = CSRMWriteM & (CSRAdrM == MCOUNTINHIBIT) & InstrValidNotFlushedM;
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assign IllegalCSRMWriteReadonlyM = CSRMWriteM & (CSRAdrM == MVENDORID | CSRAdrM == MARCHID | CSRAdrM == MIMPID | CSRAdrM == MHARTID);
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// CSRs
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flopenr #(`XLEN) MTVECreg(clk, reset, WriteMTVECM, {CSRWriteValM[`XLEN-1:2], 1'b0, CSRWriteValM[0]}, MTVEC_REGW);
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if (`S_SUPPORTED | (`U_SUPPORTED & `N_SUPPORTED)) begin:deleg // DELEG registers should exist
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flopenr #(`XLEN) MEDELEGreg(clk, reset, WriteMEDELEGM, CSRWriteValM & MEDELEG_MASK /*12'h7FF*/, MEDELEG_REGW);
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flopenr #(`XLEN) MIDELEGreg(clk, reset, WriteMIDELEGM, CSRWriteValM & MIDELEG_MASK /*12'h222*/, MIDELEG_REGW);
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end else assign {MEDELEG_REGW, MIDELEG_REGW} = 0;
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flopenr #(`XLEN) MSCRATCHreg(clk, reset, WriteMSCRATCHM, CSRWriteValM, MSCRATCH_REGW);
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flopenr #(`XLEN) MEPCreg(clk, reset, WriteMEPCM, NextEPCM, MEPC_REGW);
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flopenr #(`XLEN) MCAUSEreg(clk, reset, WriteMCAUSEM, NextCauseM, MCAUSE_REGW);
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if(`QEMU) assign MTVAL_REGW = `XLEN'b0;
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else flopenr #(`XLEN) MTVALreg(clk, reset, WriteMTVALM, NextMtvalM, MTVAL_REGW);
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flopenr #(32) MCOUNTERENreg(clk, reset, WriteMCOUNTERENM, CSRWriteValM[31:0], MCOUNTEREN_REGW);
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flopenr #(32) MCOUNTINHIBITreg(clk, reset, WriteMCOUNTINHIBITM, CSRWriteValM[31:0], MCOUNTINHIBIT_REGW);
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// Read machine mode CSRs
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// verilator lint_off WIDTH
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logic [5:0] entry;
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always_comb begin
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entry = '0;
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IllegalCSRMAccessM = !(`S_SUPPORTED | `U_SUPPORTED & `N_SUPPORTED) &
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(CSRAdrM == MEDELEG | CSRAdrM == MIDELEG); // trap on DELEG register access when no S or N-mode
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if (CSRAdrM >= PMPADDR0 & CSRAdrM < PMPADDR0 + `PMP_ENTRIES) // reading a PMP entry
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CSRMReadValM = PMPADDR_ARRAY_REGW[CSRAdrM - PMPADDR0];
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else if (CSRAdrM >= PMPCFG0 & CSRAdrM < PMPCFG0 + `PMP_ENTRIES/4) begin
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if (`XLEN==64) begin
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entry = ({CSRAdrM[11:1], 1'b0} - PMPCFG0)*4; // disregard odd entries in RV64
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CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+7],PMPCFG_ARRAY_REGW[entry+6],PMPCFG_ARRAY_REGW[entry+5],PMPCFG_ARRAY_REGW[entry+4],
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PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
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end else begin
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entry = (CSRAdrM - PMPCFG0)*4;
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CSRMReadValM = {PMPCFG_ARRAY_REGW[entry+3],PMPCFG_ARRAY_REGW[entry+2],PMPCFG_ARRAY_REGW[entry+1],PMPCFG_ARRAY_REGW[entry]};
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end
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end
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else case (CSRAdrM)
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MISA_ADR: CSRMReadValM = MISA_REGW;
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MVENDORID: CSRMReadValM = 0;
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MARCHID: CSRMReadValM = 0;
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MIMPID: CSRMReadValM = `XLEN'h100; // pipelined implementation
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MHARTID: CSRMReadValM = MHARTID_REGW; // hardwired to 0
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MSTATUS: CSRMReadValM = MSTATUS_REGW;
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MSTATUSH: CSRMReadValM = 0; // flush this out later if MBE and SBE fields are supported
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MTVEC: CSRMReadValM = MTVEC_REGW;
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MEDELEG: CSRMReadValM = MEDELEG_REGW;
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MIDELEG: CSRMReadValM = MIDELEG_REGW;
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MIP: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIP_REGW};
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MIE: CSRMReadValM = {{(`XLEN-12){1'b0}}, MIE_REGW};
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MSCRATCH: CSRMReadValM = MSCRATCH_REGW;
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MEPC: CSRMReadValM = MEPC_REGW;
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MCAUSE: CSRMReadValM = MCAUSE_REGW;
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MTVAL: CSRMReadValM = MTVAL_REGW;
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MCOUNTEREN:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTEREN_REGW};
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MCOUNTINHIBIT:CSRMReadValM = {{(`XLEN-32){1'b0}}, MCOUNTINHIBIT_REGW};
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default: begin
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CSRMReadValM = 0;
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IllegalCSRMAccessM = 1;
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end
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endcase
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end
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// verilator lint_on WIDTH
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endmodule
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