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https://github.com/openhwgroup/cvw
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178 lines
9.0 KiB
Systemverilog
178 lines
9.0 KiB
Systemverilog
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///////////////////////////////////////////
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// csrc.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Counter CSRs
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// See RISC-V Privileged Mode Specification 20190608 3.1.10-11
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module csrc #(parameter
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MHPMCOUNTERBASE = 12'hB00,
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MHPMCOUNTERHBASE = 12'hB80,
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MHPMEVENTBASE = 12'h320,
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HPMCOUNTERBASE = 12'hC00,
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HPMCOUNTERHBASE = 12'hC80,
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TIME = 12'hC01,
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TIMEH = 12'hC81
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) (
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input logic clk, reset,
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input logic StallE, StallM, StallW,
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input logic FlushE, FlushM, FlushW,
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input logic InstrValidM, LoadStallD, CSRMWriteM,
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input logic BPPredDirWrongM,
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input logic BTBPredPCWrongM,
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input logic RASPredPCWrongM,
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input logic BPPredClassNonCFIWrongM,
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input logic [4:0] InstrClassM,
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input logic DCacheMiss,
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input logic DCacheAccess,
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input logic ICacheMiss,
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input logic ICacheAccess,
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input logic [11:0] CSRAdrM,
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input logic [1:0] PrivilegeModeW,
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input logic [`XLEN-1:0] CSRWriteValM,
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input logic [31:0] MCOUNTINHIBIT_REGW, MCOUNTEREN_REGW, SCOUNTEREN_REGW,
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input logic [63:0] MTIME_CLINT,
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output logic [`XLEN-1:0] CSRCReadValM,
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output logic IllegalCSRCAccessM
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);
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if (`ZICOUNTERS_SUPPORTED) begin:counters
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(* mark_debug = "true" *) logic [63:0] CYCLE_REGW, INSTRET_REGW;
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logic [63:0] CYCLEPlusM, INSTRETPlusM;
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logic [`XLEN-1:0] NextCYCLEM, NextINSTRETM;
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logic WriteCYCLEM, WriteINSTRETM;
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logic [4:0] CounterNumM;
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logic [`XLEN-1:0] HPMCOUNTER_REGW[`COUNTERS-1:0];
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logic [`XLEN-1:0] HPMCOUNTERH_REGW[`COUNTERS-1:0];
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logic InstrValidNotFlushedM;
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logic LoadStallE, LoadStallM;
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logic [`COUNTERS-1:0] WriteHPMCOUNTERM;
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logic [`COUNTERS-1:0] CounterEvent;
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logic [63:0] HPMCOUNTERPlusM[`COUNTERS-1:0];
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logic [`XLEN-1:0] NextHPMCOUNTERM[`COUNTERS-1:0];
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genvar i;
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// Interface signals
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flopenrc #(1) LoadStallEReg(.clk, .reset, .clear(1'b0), .en(~StallE), .d(LoadStallD), .q(LoadStallE)); // don't flush the load stall during a load stall.
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flopenrc #(1) LoadStallMReg(.clk, .reset, .clear(FlushM), .en(~StallM), .d(LoadStallE), .q(LoadStallM));
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assign InstrValidNotFlushedM = InstrValidM & ~StallW & ~FlushW;
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// Determine when to increment each counter
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assign CounterEvent[0] = 1'b1; // MCYCLE always increments
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assign CounterEvent[1] = 1'b0; // Counter 1 doesn't exist
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assign CounterEvent[2] = InstrValidNotFlushedM;
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if(`QEMU) begin: cevent // No other performance counters in QEMU
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assign CounterEvent[`COUNTERS-1:3] = 0;
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end else begin: cevent // User-defined counters
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assign CounterEvent[3] = LoadStallM; // don't want to suppress on flush as this only happens if flushed.
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assign CounterEvent[4] = BPPredDirWrongM & InstrValidNotFlushedM;
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assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM;
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assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[7] = (InstrClassM[4] | InstrClassM[2] | InstrClassM[1]) & InstrValidNotFlushedM;
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assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM;
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assign CounterEvent[9] = InstrClassM[3] & InstrValidNotFlushedM;
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assign CounterEvent[10] = BPPredClassNonCFIWrongM & InstrValidNotFlushedM;
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assign CounterEvent[11] = DCacheAccess;
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assign CounterEvent[12] = DCacheMiss;
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assign CounterEvent[13] = ICacheAccess;
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assign CounterEvent[14] = ICacheMiss;
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assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
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end
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// Counter update and write logic
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for (i = 0; i < `COUNTERS; i = i+1) begin:cntr
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assign WriteHPMCOUNTERM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERBASE + i);
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assign NextHPMCOUNTERM[i][`XLEN-1:0] = WriteHPMCOUNTERM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][`XLEN-1:0];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTER_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERM[i];
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if (`XLEN==32) begin // write high and low separately
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logic [`COUNTERS-1:0] WriteHPMCOUNTERHM;
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logic [`XLEN-1:0] NextHPMCOUNTERHM[`COUNTERS-1:0];
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assign HPMCOUNTERPlusM[i] = {HPMCOUNTERH_REGW[i], HPMCOUNTER_REGW[i]} + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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assign WriteHPMCOUNTERHM[i] = CSRMWriteM & (CSRAdrM == MHPMCOUNTERHBASE + i);
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assign NextHPMCOUNTERHM[i] = WriteHPMCOUNTERHM[i] ? CSRWriteValM : HPMCOUNTERPlusM[i][63:32];
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always_ff @(posedge clk) //, posedge reset) // ModelSim doesn't like syntax of passing array element to flop
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if (reset) HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 0;
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else HPMCOUNTERH_REGW[i][`XLEN-1:0] <= #1 NextHPMCOUNTERHM[i];
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end else begin // XLEN=64; write entire register
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assign HPMCOUNTERPlusM[i] = HPMCOUNTER_REGW[i] + {63'b0, CounterEvent[i] & ~MCOUNTINHIBIT_REGW[i]};
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end
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end
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// Read Counters, or cause excepiton if insufficient privilege in light of COUNTEREN flags
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assign CounterNumM = CSRAdrM[4:0]; // which counter to read?
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always_comb
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if (PrivilegeModeW == `M_MODE |
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MCOUNTEREN_REGW[CounterNumM] & (!`S_SUPPORTED | PrivilegeModeW == `S_MODE | SCOUNTEREN_REGW[CounterNumM])) begin
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IllegalCSRCAccessM = 0;
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if (`XLEN==64) begin // 64-bit counter reads
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// Veri lator doesn't realize this only occurs for XLEN=64
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/* verilator lint_off WIDTH */
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT; // TIME register is a shadow of the memory-mapped MTIME from the CLINT
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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end
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end else begin // 32-bit counter reads
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// Veri lator doesn't realize this only occurs for XLEN=32
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/* verilator lint_off WIDTH */
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if (CSRAdrM == TIME) CSRCReadValM = MTIME_CLINT[31:0];// TIME register is a shadow of the memory-mapped MTIME from the CLINT
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else if (CSRAdrM == TIMEH) CSRCReadValM = MTIME_CLINT[63:32];
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/* verilator lint_on WIDTH */
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else if (CSRAdrM >= MHPMCOUNTERBASE & CSRAdrM < MHPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERBASE & CSRAdrM < HPMCOUNTERBASE+`COUNTERS) CSRCReadValM = HPMCOUNTER_REGW[CounterNumM];
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else if (CSRAdrM >= MHPMCOUNTERHBASE & CSRAdrM < MHPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else if (CSRAdrM >= HPMCOUNTERHBASE & CSRAdrM < HPMCOUNTERHBASE+`COUNTERS) CSRCReadValM = HPMCOUNTERH_REGW[CounterNumM];
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else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // requested CSR doesn't exist
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end
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end
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end else begin
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CSRCReadValM = 0;
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IllegalCSRCAccessM = 1; // no privileges for this csr
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end
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end else begin
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assign CSRCReadValM = 0;
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assign IllegalCSRCAccessM = 1; // counters aren't enabled
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end
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endmodule
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// To Do:
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// review couunter spec
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// upper unimplemented counters should read as 0 rather than illegal access
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// mounteren should only exist if u-mode exists
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// Implement MHPMEVENT
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