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319 lines
20 KiB
Systemverilog
319 lines
20 KiB
Systemverilog
///////////////////////////////////////////
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// controller.sv
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//
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// Written: David_Harris@hmc.edu, Sarah.Harris@unlv.edu
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// Created: 9 January 2021
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// Modified:
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//
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// Purpose: Top level controller module
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Section 4.1.4, Figure 4.8, Table 4.5)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module controller(
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input logic clk, reset,
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// Decode stage control signals
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input logic StallD, FlushD, // Stall, flush Decode stage
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input logic [31:0] InstrD, // Instruction in Decode stage
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output logic [2:0] ImmSrcD, // Type of immediate extension
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input logic IllegalIEUFPUInstrD, // Illegal IEU and FPU instruction
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output logic IllegalBaseInstrD, // Illegal I-type instruction, or illegal RV32 access to upper 16 registers
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output logic JumpD, // Jump instruction
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output logic BranchD, // Branch instruction
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// Execute stage control signals
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input logic StallE, FlushE, // Stall, flush Execute stage
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input logic [1:0] FlagsE, // Comparison flags ({eq, lt})
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input logic FWriteIntE, // Write integer register, coming from FPU controller
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output logic PCSrcE, // Select signal to choose next PC (for datapath and Hazard unit)
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output logic [2:0] ALUControlE, // ALU operation to perform
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output logic ALUSrcAE, ALUSrcBE, // ALU operands
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output logic ALUResultSrcE, // Selects result to pass on to Memory stage
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output logic [2:0] ALUSelectE, // ALU mux select signal
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output logic MemReadE, CSRReadE, // Instruction reads memory, reads a CSR (needed for Hazard unit)
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output logic [2:0] Funct3E, // Instruction's funct3 field
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output logic IntDivE, // Integer divide
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output logic MDUE, // MDU (multiply/divide) operatio
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output logic W64E, // RV64 W-type operation
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output logic JumpE, // jump instruction
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output logic BranchE, // Branch instruction
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output logic SCE, // Store Conditional instruction
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output logic BranchSignedE, // Branch comparison operands are signed (if it's a branch)
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output logic [3:0] BSelectE, // One-Hot encoding of if it's ZBA_ZBB_ZBC_ZBS instruction
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output logic [2:0] ZBBSelectE, // ZBB mux select signal in Execute stage
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// Memory stage control signals
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input logic StallM, FlushM, // Stall, flush Memory stage
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output logic [1:0] MemRWM, // Mem read/write: MemRWM[1] = 1 for read, MemRWM[0] = 1 for write
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output logic CSRReadM, CSRWriteM, PrivilegedM, // CSR read, write, or privileged instruction
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output logic [1:0] AtomicM, // Atomic (AMO) instruction
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output logic [2:0] Funct3M, // Instruction's funct3 field
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output logic RegWriteM, // Instruction writes a register (needed for Hazard unit)
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output logic InvalidateICacheM, FlushDCacheM, // Invalidate I$, flush D$
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output logic InstrValidD, InstrValidE, InstrValidM, // Instruction is valid
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output logic FenceM, // Fence instruction
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output logic FWriteIntM, // FPU controller writes integer register file
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// Writeback stage control signals
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input logic StallW, FlushW, // Stall, flush Writeback stage
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output logic RegWriteW, IntDivW, // Instruction writes a register, is an integer divide
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output logic [2:0] ResultSrcW, // Select source of result to write back to register file
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// Stall during CSRs
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output logic CSRWriteFenceM, // CSR write or fence instruction; needs to flush the following instructions
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output logic StoreStallD // Store (memory write) causes stall
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);
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logic [6:0] OpD; // Opcode in Decode stage
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logic [2:0] Funct3D; // Funct3 field in Decode stage
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logic [6:0] Funct7D; // Funct7 field in Decode stage
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logic [4:0] Rs1D; // Rs1 source register in Decode stage
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`define CTRLW 23
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// pipelined control signals
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logic RegWriteD, RegWriteE; // RegWrite (register will be written)
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logic [2:0] ResultSrcD, ResultSrcE, ResultSrcM; // Select which result to write back to register file
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logic [1:0] MemRWD, MemRWE; // Store (write to memory)
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logic ALUOpD; // 0 for address generation, 1 for all other operations (must use Funct3)
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logic BaseALUOpD, BaseW64D; // ALU operation and W64 for Base instructions specifically
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logic BaseRegWriteD; // Indicates if Base instruction register write instruction
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logic BaseSubArithD; // Indicates if Base instruction subtracts, sra, slt, sltu
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logic [2:0] ALUControlD; // Determines ALU operation
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logic [2:0] ALUSelectD; // ALU mux select signal
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logic ALUSrcAD, ALUSrcBD; // ALU inputs
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logic ALUResultSrcD, W64D, MDUD; // ALU result, is RV64 W-type, is multiply/divide instruction
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logic CSRZeroSrcD; // Ignore setting and clearing zeros to CSR
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logic CSRReadD; // CSR read instruction
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logic [1:0] AtomicD; // Atomic (AMO) instruction
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logic FenceXD; // Fence instruction
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logic InvalidateICacheD, FlushDCacheD;// Invalidate I$, flush D$
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logic CSRWriteD, CSRWriteE; // CSR write
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logic PrivilegedD, PrivilegedE; // Privileged instruction
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logic InvalidateICacheE, FlushDCacheE;// Invalidate I$, flush D$
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logic [`CTRLW-1:0] ControlsD; // Main Instruction Decoder control signals
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logic SubArithD; // TRUE for R-type subtracts and sra, slt, sltu or B-type ext clr, andn, orn, xnor
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logic subD, sraD, sltD, sltuD; // Indicates if is one of these instructions
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logic maxE, maxuE, minE, minuE; // Indicates if is one of these instructions in Execute Stage
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logic BranchTakenE; // Branch is taken
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logic eqE, ltE; // Comparator outputs
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logic unused;
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logic BranchFlagE; // Branch flag to use (chosen between eq or lt)
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logic IEURegWriteE; // Register write
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logic BRegWriteE; // Register write from BMU controller in Execute Stage
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logic IllegalERegAdrD; // RV32E attempts to write upper 16 registers
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logic IllegalBitmanipInstrD; // Unrecognized B instruction
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logic [1:0] AtomicE; // Atomic instruction
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logic FenceD, FenceE; // Fence instruction
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logic SFenceVmaD; // sfence.vma instruction
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logic IntDivM; // Integer divide instruction
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logic [3:0] BSelectD; // One-Hot encoding if it's ZBA_ZBB_ZBC_ZBS instruction in decode stage
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logic [2:0] ZBBSelectD; // ZBB Mux Select Signal
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logic BRegWriteD; // Indicates if it is a R type B instruction in decode stage
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logic BW64D; // Indiciates if it is a W type B instruction in decode stage
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logic BALUOpD; // Indicates if it is an ALU B instruction in decode stage
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logic BSubArithD; // TRUE for B-type ext, clr, andn, orn, xnor
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// Extract fields
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assign OpD = InstrD[6:0];
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assign Funct3D = InstrD[14:12];
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assign Funct7D = InstrD[31:25];
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assign Rs1D = InstrD[19:15];
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// Main Instruction Decoder
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always_comb
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case(OpD)
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// RegWrite_ImmSrc_ALUSrc_MemRW_ResultSrc_Branch_BaseALUOp_Jump_ALUResultSrc_W64_CSRRead_Privileged_Fence_MDU_Atomic_Illegal
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7'b0000000: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Illegal instruction
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7'b0000011: ControlsD = `CTRLW'b1_000_01_10_001_0_0_0_0_0_0_0_0_0_00_0; // lw
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7'b0000111: ControlsD = `CTRLW'b0_000_01_10_001_0_0_0_0_0_0_0_0_0_00_1; // flw - only legal if FP supported
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7'b0001111: if (`ZIFENCEI_SUPPORTED)
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_1_0_00_0; // fence
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_0; // fence treated as nop
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7'b0010011: ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_0_0_0_0_0_00_0; // I-type ALU
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7'b0010111: ControlsD = `CTRLW'b1_100_11_00_000_0_0_0_0_0_0_0_0_0_00_0; // auipc
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7'b0011011: if (`XLEN == 64)
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ControlsD = `CTRLW'b1_000_01_00_000_0_1_0_0_1_0_0_0_0_00_0; // IW-type ALU for RV64i
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0100011: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_0; // sw
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7'b0100111: ControlsD = `CTRLW'b0_001_01_01_000_0_0_0_0_0_0_0_0_0_00_1; // fsw - only legal if FP supported
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7'b0101111: if (`A_SUPPORTED) begin
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if (InstrD[31:27] == 5'b00010)
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ControlsD = `CTRLW'b1_000_00_10_001_0_0_0_0_0_0_0_0_0_01_0; // lr
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else if (InstrD[31:27] == 5'b00011)
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ControlsD = `CTRLW'b1_101_01_01_100_0_0_0_0_0_0_0_0_0_01_0; // sc
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else
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ControlsD = `CTRLW'b1_101_01_11_001_0_0_0_0_0_0_0_0_0_10_0; // amo
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0110011: if (Funct7D == 7'b0000000 | Funct7D == 7'b0100000)
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_0_0_0_0_0_00_0; // R-type
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else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])))
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_0_0_0_0_1_00_0; // Multiply/divide
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b0110111: ControlsD = `CTRLW'b1_100_01_00_000_0_0_0_1_0_0_0_0_0_00_0; // lui
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7'b0111011: if ((Funct7D == 7'b0000000 | Funct7D == 7'b0100000) & `XLEN == 64)
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ControlsD = `CTRLW'b1_000_00_00_000_0_1_0_0_1_0_0_0_0_00_0; // R-type W instructions for RV64i
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else if (Funct7D == 7'b0000001 & (`M_SUPPORTED | (`ZMMUL_SUPPORTED & ~Funct3D[2])) & `XLEN == 64)
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ControlsD = `CTRLW'b1_000_00_00_011_0_0_0_0_1_0_0_0_1_00_0; // W-type Multiply/Divide
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else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // Non-implemented instruction
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7'b1100011: ControlsD = `CTRLW'b0_010_11_00_000_1_0_0_0_0_0_0_0_0_00_0; // branches
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7'b1100111: ControlsD = `CTRLW'b1_000_01_00_000_0_0_1_1_0_0_0_0_0_00_0; // jalr
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7'b1101111: ControlsD = `CTRLW'b1_011_11_00_000_0_0_1_1_0_0_0_0_0_00_0; // jal
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7'b1110011: if (`ZICSR_SUPPORTED) begin
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if (Funct3D == 3'b000)
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_1_0_0_00_0; // privileged; decoded further in priveleged modules
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else
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ControlsD = `CTRLW'b1_000_00_00_010_0_0_0_0_0_1_0_0_0_00_0; // csrs
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end else
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ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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default: ControlsD = `CTRLW'b0_000_00_00_000_0_0_0_0_0_0_0_0_0_00_1; // non-implemented instruction
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endcase
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// Unswizzle control bits
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// Squash control signals if coming from an illegal compressed instruction
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// On RV32E, can't write to upper 16 registers. Checking reads to upper 16 is more costly so disregard them.
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assign IllegalERegAdrD = `E_SUPPORTED & `ZICSR_SUPPORTED & ControlsD[`CTRLW-1] & InstrD[11];
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assign IllegalBaseInstrD = (ControlsD[0] & IllegalBitmanipInstrD) | IllegalERegAdrD ; //NOTE: Do we want to segregate the IllegalBitmanipInstrD into its own output signal
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//assign IllegalBaseInstrD = 1'b0;
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assign {BaseRegWriteD, ImmSrcD, ALUSrcAD, ALUSrcBD, MemRWD,
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ResultSrcD, BranchD, BaseALUOpD, JumpD, ALUResultSrcD, BaseW64D, CSRReadD,
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PrivilegedD, FenceXD, MDUD, AtomicD, unused} = IllegalIEUFPUInstrD ? `CTRLW'b0 : ControlsD;
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// If either bitmanip signal or base instruction signal
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assign ALUOpD = BaseALUOpD | BALUOpD;
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assign RegWriteD = BaseRegWriteD | BRegWriteD;
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assign W64D = BaseW64D | BW64D;
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assign SubArithD = BaseSubArithD | BSubArithD; // TRUE If B-type or R-type instruction involves inverted operand
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assign CSRZeroSrcD = InstrD[14] ? (InstrD[19:15] == 0) : (Rs1D == 0); // Is a CSR instruction using zero as the source?
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assign CSRWriteD = CSRReadD & !(CSRZeroSrcD & InstrD[13]); // Don't write if setting or clearing zeros
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assign SFenceVmaD = PrivilegedD & (InstrD[31:25] == 7'b0001001);
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assign FenceD = SFenceVmaD | FenceXD; // possible sfence.vma or fence.i
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//NOTE: Move the B conditional logic into bctrl
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if (`ZBA_SUPPORTED) begin
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// ALU Decoding is more comprehensive when ZBA is supported. slt and slti conflicts with sh1add, sh1add.uw
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assign sltD = (Funct3D == 3'b010 & (~(Funct7D[4]) | ~OpD[5])) ;
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end else begin
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assign sltD = (Funct3D == 3'b010);
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end
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if (`ZBB_SUPPORTED) begin
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// we only need these signals if we want to calculate a signedD flag in decode stage to pass to the comparator.
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assign maxE = (Funct3E[1:0] == 2'b10 & BSelectE[2]);
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assign maxuE = (Funct3E[1:0] == 2'b11 & BSelectE[2]);
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assign minE = (Funct3E[1:0] == 2'b00 & BSelectE[2]);
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assign minuE = (Funct3E[1:0] == 2'b01 & BSelectE[2]);
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end else begin
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assign maxE = 0;
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assign maxuE = 0;
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assign minE = 0;
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assign minuE = 0;
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end
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// ALU Decoding is lazy, only using func7[5] to distinguish add/sub and srl/sra
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assign sltuD = (Funct3D == 3'b011);
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assign subD = (Funct3D == 3'b000 & Funct7D[5] & OpD[5]); // OpD[5] needed to distinguish sub from addi
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assign sraD = (Funct3D == 3'b101 & Funct7D[5]);
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assign BaseSubArithD = ALUOpD & (subD | sraD | sltD | sltuD);
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assign ALUControlD = {W64D, SubArithD, ALUOpD};
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// BITMANIP Configuration Block
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if (`ZBS_SUPPORTED | `ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED) begin: bitmanipi //change the conditional expression to OR any Z supported flags
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bmuctrl bmuctrl(.clk, .reset, .StallD, .FlushD, .InstrD, .ALUSelectD, .BSelectD, .ZBBSelectD, .BRegWriteD, .BW64D, .BALUOpD, .BSubArithD, .IllegalBitmanipInstrD, .StallE, .FlushE, .ALUSelectE, .BSelectE, .ZBBSelectE, .BRegWriteE);
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//assign SubArithD = (ALUOpD) & (subD | sraD | sltD | sltuD | (`ZBS_SUPPORTED & (bextD | bclrD)) | (`ZBB_SUPPORTED & (andnD | ornD | xnorD))); // TRUE for R-type subtracts and sra, slt, sltu, and any B instruction that requires inverted operand
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end else begin: bitmanipi
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assign ALUSelectD = Funct3D;
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assign ALUSelectE = Funct3E;
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assign BSelectE = 4'b0000;
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assign BSelectD = 4'b0000;
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assign ZBBSelectE = 3'b000;
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assign BRegWriteD = 1'b0;
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assign BW64D = 1'b0;
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assign BALUOpD = 1'b0;
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assign BRegWriteE = 1'b0;
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assign BSubArithD = 1'b0;
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assign IllegalBitmanipInstrD = 1'b1;
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end
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// Fences
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// Ordinary fence is presently a nop
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// fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
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if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei
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logic FenceID;
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assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
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assign InvalidateICacheD = FenceID;
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assign FlushDCacheD = FenceID;
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end else begin:fencei
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assign InvalidateICacheD = 0;
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assign FlushDCacheD = 0;
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end
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// Decocde stage pipeline control register
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flopenrc #(1) controlregD(clk, reset, FlushD, ~StallD, 1'b1, InstrValidD);
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// Execute stage pipeline control register and logic
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flopenrc #(28) controlregE(clk, reset, FlushE, ~StallE,
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{RegWriteD, ResultSrcD, MemRWD, JumpD, BranchD, ALUControlD, ALUSrcAD, ALUSrcBD, ALUResultSrcD, CSRReadD, CSRWriteD, PrivilegedD, Funct3D, W64D, MDUD, AtomicD, InvalidateICacheD, FlushDCacheD, FenceD, InstrValidD},
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{IEURegWriteE, ResultSrcE, MemRWE, JumpE, BranchE, ALUControlE, ALUSrcAE, ALUSrcBE, ALUResultSrcE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, W64E, MDUE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE});
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// Branch Logic
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// The comparator handles both signed and unsigned branches using BranchSignedE
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// Hence, only eq and lt flags are needed
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assign BranchSignedE = (~(Funct3E[2:1] == 2'b11) & ~BSelectE[2]) | (`ZBB_SUPPORTED & (maxE | minE)) ;
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//assign BranchSignedE = ~(Funct3E[2:1] == 2'b11);
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assign {eqE, ltE} = FlagsE;
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mux2 #(1) branchflagmux(eqE, ltE, Funct3E[2], BranchFlagE);
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assign BranchTakenE = BranchFlagE ^ Funct3E[0];
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assign PCSrcE = JumpE | BranchE & BranchTakenE;
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// Other execute stage controller signals
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assign MemReadE = MemRWE[1];
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assign SCE = (ResultSrcE == 3'b100);
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assign RegWriteE = IEURegWriteE | FWriteIntE; // IRF register writes could come from IEU or FPU controllers
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assign IntDivE = MDUE & Funct3E[2]; // Integer division operation
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// Memory stage pipeline control register
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flopenrc #(20) controlregM(clk, reset, FlushM, ~StallM,
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{RegWriteE, ResultSrcE, MemRWE, CSRReadE, CSRWriteE, PrivilegedE, Funct3E, FWriteIntE, AtomicE, InvalidateICacheE, FlushDCacheE, FenceE, InstrValidE, IntDivE},
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{RegWriteM, ResultSrcM, MemRWM, CSRReadM, CSRWriteM, PrivilegedM, Funct3M, FWriteIntM, AtomicM, InvalidateICacheM, FlushDCacheM, FenceM, InstrValidM, IntDivM});
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// Writeback stage pipeline control register
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flopenrc #(5) controlregW(clk, reset, FlushW, ~StallW,
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{RegWriteM, ResultSrcM, IntDivM},
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{RegWriteW, ResultSrcW, IntDivW});
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// Flush F, D, and E stages on a CSR write or Fence.I or SFence.VMA
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assign CSRWriteFenceM = CSRWriteM | FenceM;
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// assign CSRWriteFencePendingDEM = CSRWriteD | CSRWriteE | CSRWriteM | FenceD | FenceE | FenceM;
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// the synchronous DTIM cannot read immediately after write
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// a cache cannot read or write immediately after a write
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assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
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endmodule |