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72 lines
2.2 KiB
Systemverilog
72 lines
2.2 KiB
Systemverilog
///////////////////////////////////////////
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// zbc.sv
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//
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// Written: Kevin Kim <kekim@hmc.edu> and Kip Macsai-Goren <kmacsaigoren@hmc.edu>
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// Created: 2 February 2023
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// Modified:
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//
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// Purpose: RISC-V single bit manipulation unit (ZBC instructions)
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//
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// Documentation: RISC-V System on Chip Design Chapter ***
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module zbc #(parameter WIDTH=32) (
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input logic [WIDTH-1:0] A, B, // Operands
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input logic [2:0] Funct3, // Indicates operation to perform
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output logic [WIDTH-1:0] ZBCResult); // ZBC result
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logic [WIDTH-1:0] ClmulResult, RevClmulResult;
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logic [WIDTH-1:0] RevA, RevB;
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logic [WIDTH-1:0] x,y;
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bitreverse #(WIDTH) brA(.a(A), .b(RevA));
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bitreverse #(WIDTH) brB(.a(B), .b(RevB));
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// zbc input select mux
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always_comb begin
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casez (Funct3[1:0])
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2'b01: begin //clmul
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x = A;
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y = B;
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end
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2'b11: begin //clmulh
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x = {RevA[WIDTH-2:0], {1'b0}};
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y = {{1'b0}, RevB[WIDTH-2:0]};
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end
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2'b10: begin //clmulr
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x = RevA;
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y = RevB;
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end
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default: begin
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x = 0;
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y = 0;
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end
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endcase
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end
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clmul #(WIDTH) clm(.A(x), .B(y), .ClmulResult(ClmulResult));
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bitreverse #(WIDTH) brClmulResult(.a(ClmulResult), .b(RevClmulResult));
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assign ZBCResult = (Funct3[1]) ? RevClmulResult : ClmulResult;
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endmodule |