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98 lines
3.8 KiB
Systemverilog
98 lines
3.8 KiB
Systemverilog
///////////////////////////////////////////
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// mmu.sv
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//
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// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
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// Modified:
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//
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// Purpose: Memory management unit, including TLB, PMA, PMP
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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// The TLB will have 2**ENTRY_BITS total entries
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module mmu #(parameter ENTRY_BITS = 3,
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parameter IMMU = 0) (
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input logic clk, reset,
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// Current value of satp CSR (from privileged unit)
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input logic [`XLEN-1:0] SATP_REGW,
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input logic STATUS_MXR, STATUS_SUM,
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// Current privilege level of the processeor
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input logic [1:0] PrivilegeModeW,
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// 00 - TLB is not being accessed
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// 1x - TLB is accessed for a read (or an instruction)
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// x1 - TLB is accessed for a write
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// 11 - TLB is accessed for both read and write
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input logic [1:0] TLBAccessType,
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input logic DisableTranslation,
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// Virtual address input
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input logic [`XLEN-1:0] VirtualAddress,
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input logic [1:0] Size, // 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
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// Controls for writing a new entry to the TLB
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input logic [`XLEN-1:0] PTEWriteVal,
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input logic [1:0] PageTypeWriteVal,
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input logic TLBWrite,
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// Invalidate all TLB entries
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input logic TLBFlush,
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// Physical address outputs
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output logic [`PA_BITS-1:0] PhysicalAddress,
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output logic TLBMiss,
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output logic TLBHit,
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// Faults
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output logic TLBPageFault,
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// PMA checker signals
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM,
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input var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0],
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input var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0],
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output logic SquashBusAccess, // *** send to privileged unit
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output logic PMPInstrAccessFaultF, PMPLoadAccessFaultM, PMPStoreAccessFaultM,
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output logic PMAInstrAccessFaultF, PMALoadAccessFaultM, PMAStoreAccessFaultM
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// output logic [5:0] SelRegions
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);
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logic PMPSquashBusAccess, PMASquashBusAccess;
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logic Cacheable, Idempotent, AtomicAllowed; // *** here so that the pmachecker has somewhere to put these outputs. *** I'm leaving them as outputs to pma checker, but I'm stopping them here.
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// Translation lookaside buffer
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tlb #(.ENTRY_BITS(ENTRY_BITS), .ITLB(IMMU)) tlb(.*);
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///////////////////////////////////////////
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// Check physical memory accesses
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///////////////////////////////////////////
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pmachecker pmachecker(.*);
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pmpchecker pmpchecker(.*);
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assign SquashBusAccess = PMASquashBusAccess || PMPSquashBusAccess;
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endmodule
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