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Configurable RISC-V Processor
17 Commits 4 Branches 2 Tags 52 MiB
SystemVerilog 33.8%
Python 19.2%
Assembly 17.5%
Tcl 16.2%
C 5.8%
Other 7.4%
5b0070ac0b
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Noah Boorstin 5b0070ac0b Start adding register checking 
I'm now realizing we need to simulate loads, or else these will all be wrong
2021-01-22 15:11:13 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined Start adding register checking 2021-01-22 15:11:13 -05:00
.gitignore load instructions from file line by line 2021-01-22 14:11:17 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor