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63 lines
2.4 KiB
Systemverilog
63 lines
2.4 KiB
Systemverilog
///////////////////////////////////////////
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//
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// Written: me@KatherineParry.com
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// Modified: 7/5/2022
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//
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// Purpose: calculating the result's sign
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module resultsign(
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input logic [2:0] Frm,
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input logic FmaPs, FmaAs,
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input logic ZInf,
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input logic InfIn,
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input logic FmaOp,
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input logic [`NE+1:0] FmaSe,
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input logic FmaSZero,
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input logic Mult,
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input logic R,
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input logic S,
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input logic Ms,
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output logic Ws
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);
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logic Zeros;
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logic Infs;
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// Determine the sign if the sum is zero
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// if cancelation then 0 unless round to -infinity
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// if multiply then Psgn
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// otherwise psign
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assign Zeros = (FmaPs^FmaAs)&~(FmaSe[`NE+1] | ((FmaSe == 0) & (R|S)))&~Mult ? Frm[1:0] == 2'b10 : FmaPs;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Infs = ZInf ? FmaAs : FmaPs;
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assign Ws = InfIn&FmaOp ? Infs : FmaSZero&FmaOp ? Zeros : Ms;
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endmodule |