Rose Thompson 1345a0f315 Merge branch 'main' of https://github.com/openhwgroup/cvw		2024-09-24 10:13:50 -05:00
..
axi_sdc_controller.v	Changed SDC outputs to ensure they are aligned to the falling edge of the divided down clock rather than the processor clock.	2023-10-10 17:46:12 -05:00
fpgaTop.sv	Modified fpga config to support two fpga boards with different amount of memory.	2024-08-29 16:12:58 -07:00
fpgaTopArtyA7.sv	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-09-24 10:13:50 -05:00
wallypipelinedsocwrapper.sv	Updated my name in multiple locations.	2024-08-21 10:50:39 -07:00