cvw/pipelined/src/fpu
2022-12-30 09:56:35 -06:00
..
fdivsqrt continued simplifying integer division special cases 2022-12-30 07:40:28 -08:00
fma minor optimizations and renaming 2022-12-29 15:54:17 -06:00
postproc one bitt removed from inital lignment shift 2022-12-28 17:46:53 -06:00
fclassify.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fcmp.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fctrl.sv Fixed floating Sqrt signal when floating point is disabled, causing REMU tohang during buildroot around 3.2M 2022-12-27 21:24:38 -08:00
fcvt.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fhazard.sv Removed XEnE, YEnE, and ZEnE from forward logic. 2022-12-23 14:27:03 -06:00
fpu.sv minor optimizations and renaming 2022-12-29 15:54:17 -06:00
fregfile.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
fsgninj.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
normshift.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpack.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00
unpackinput.sv Partitioned fdivsqrt into one module per file and added file names to opening comments 2022-09-20 03:57:57 -07:00