mirror of
https://github.com/openhwgroup/cvw
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100 lines
2.1 KiB
Systemverilog
100 lines
2.1 KiB
Systemverilog
// ppa.sv
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// Teo Ene & David_Harris@hmc.edu 25 Feb 2021
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// Measure PPA of various building blocks
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module top(
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input logic a1,
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input logic [7:0] a8, b8,
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input logic [15:0] a16, b16,
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input logic [31:0] a32, b32,
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input logic [63:0] a64, b64,
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output logic yinv,
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output logic [63:0] y1, y2, y3, y4
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);
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// fo4 inverter
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myinv myinv(a1, yinv);)
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// adders
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add #(8) add8(a8, b8, yadd8);
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add #(16) add16(a16, b16, yadd16);
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add #(32) add32(a32, b32, yadd32);
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add #(64) add64(a64, b64, yadd64);
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// mux2, mux3, mux4 of 1, 8, 16, 32, 64
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endmodule
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module myinv(input a, output y);
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driver #(1) drive(a, in1);
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assign out = ~in;
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load #(1) load(out, y);
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endmodule
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module add #(parameter WIDTH=8) (
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input logic [7:0] a, b,
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output logic [7:0] y
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);
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logic [WIDTH-1:0] in1, in2, out;
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driver #(WIDTH) drive1(a, in1);
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driver #(WIDTH) drive2(b, in2);
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assign out = in1 + in2;
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load #(WIDTH) load(out, y);
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endmodule
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module INVX2(input logic a, output logic y);
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generate
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if (LIB == SKY130)
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sky130_osu_sc_12T_ms__inv_2 inv(a, y);
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else if (LIB == SKL90)
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scc9gena_inv_2 inv(a, y)
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else if (LIB == GF14)
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INV_X2N_A10P5PP84TSL_C14(a, y)
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endgenerate
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endmodule
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module driver #(parameter WDITH=1) (
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input [WIDTH-1:0] logic a,
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output [WIDTH-1:0] logic y
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);
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logic [WIDTH-1:0] ab;
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INVX2 i1[WIDTH-1:0](a, ab);
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INVX2 i2[WIDTH-1:0](ab, y);
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endmodule
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module inv4(input logic a, output logic y);
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logic [3:0] b
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INVX2 i0(a, b[0]);
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INVX2 i1(a, b[1]);
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INVX2 i2(a, b[2]);
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INVX2 i3(a, b[3]);
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INVX2 i00(b[0], y;
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INVX2 i01(b[0], y);
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INVX2 i02(b[0], y);
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INVX2 i03(b[0], y);
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INVX2 i10(b[1], y;
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INVX2 i11(b[1], y);
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INVX2 i12(b[1], y);
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INVX2 i13(b[1], y);
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INVX2 i20(b[2], y;
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INVX2 i21(b[2], y);
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INVX2 i22(b[2], y);
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INVX2 i23(b[2], y);
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INVX2 i30(b[3], y;
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INVX2 i31(b[3], y);
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INVX2 i32(b[3], y);
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INVX2 i33(b[3], y);
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endmodule
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module load #(parameter WDITH=1) (
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input [WIDTH-1:0] logic a,
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output [WIDTH-1:0] logic y
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);
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logic [WIDTH-1:0] ab;
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inv4 load[WIDTH-1:0](a, y);
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endmodule
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