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cvw/synthDC
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Kevin Kim 53fc6e1ca7 removed duplicate synth scripts
2023-08-29 08:25:31 -07:00
..
ppa installation script update 2023-03-23 09:31:17 -07:00
scripts removed duplicate synth scripts 2023-08-29 08:25:31 -07:00
.synopsys_dc.setup Slight tweak to .synopsys for OSU setup 2023-02-23 07:52:40 -06:00
extractArea.pl touched extractArea.pl 2023-02-20 11:18:31 -08:00
extractSummary.py Extraction script updates to match new reports names 2023-02-20 10:16:45 -08:00
Makefile removed duplicate synth scripts 2023-08-29 08:25:31 -07:00
README.md Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
wallySynth.py Added noAtomic feature to swweep 2023-02-19 20:05:39 -08:00

README.md

Synthesis for RISC-V Microprocessor System-on-Chip Design

This subdirectory contains synthesis scripts for use with Synopsys (snps) Design Compiler (DC). Synthesis commands are found in scripts/synth.tcl.

Example Usage make synth DESIGN=wallypipelinedcore FREQ=500

environment variables

DESIGN Design provides the name of the output log. Default is synth.

FREQ Frequency in MHz. Default is 500

CONFIG The Wally configuration file. The default is rv32e. Examples: rv32e, rv64gc, rv32gc

TECH The target standard cell library. The default is sky130. sky90: skywater 90nm TT 25C sky130: skywater 130nm TT 25C

SAIFPOWER Controls if power analysis is driven by switching factor or RTL modelsim simulation. When enabled requires a saif file named power.saif. The default is 0. 0: switching factor power analysis 1: RTL simulation driven power analysis.