cvw/wally-pipelined/src/ieu
Ross Thompson 619bbd9d83 Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
2021-03-04 13:35:46 -06:00
..
alu.sv Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
controller.sv Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
datapath.sv Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
extend.sv Initial (untested) implementation of lr and sc 2021-03-01 00:09:45 -05:00
forward.sv Eliminated flushing pipeline on CSR reads 2021-02-26 17:00:07 -05:00
ieu.sv Merge branch 'bp' into main 2021-03-04 13:35:46 -06:00
regfile.sv Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
shifter.sv Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00