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https://github.com/openhwgroup/cvw
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132 lines
3.9 KiB
ArmAsm
132 lines
3.9 KiB
ArmAsm
// trap.S
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// David_Harris@hmc.edu 11 May 2022
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//
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// Demonstrates setting up traps and invoking a trap handler.
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// The trap handler accepts timer interrupts and ecalls.
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// Saves cause and mtval into the signature
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// Ecall takes one argument in a0
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// 0: change privilege mode to user
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// 1: change privilege mode to supervisor
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// 3: change privilege mode to machine
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// 4: exit program with write tohost
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.EQU MTIME, 0x200bff8
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.EQU MTIMECMP, 0x2004000
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.global rvtest_entry_point
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rvtest_entry_point:
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la sp, topofstack # Initialize stack pointer (not used)
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la s6, begin_signature # s6 points to signature
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# Set up timer
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jal set_timecmp
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# Set up interrupts
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la t0, trap_handler
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csrw mtvec, t0 # Initialize MTVEC to trap_handler
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csrw mideleg, zero # Don't delegate interrupts
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csrw medeleg, zero # Don't delegate exceptions
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li t0, 0x080
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csrw mie, t0 # Enable machine timer interrupt
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la t0, topoftrapstack
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csrw mscratch, t0 # MSCRATCH holds trap stack pointer
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csrsi mstatus, 0x8 # Turn on mstatus.MIE global interrupt enable
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main:
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# Change to user mode
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li a0, 0 # a0 = 0: argument to enter user mode
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ecall # System call to enter user mode
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# Wait for timer interrupts
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li t0, 0x1000 # loop counter start value
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loop:
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addi t0, t0, -1 # decrement counter
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bne t0, zero, loop # and repeat until zero
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done:
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li a0, 4 # argument to finish program
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ecall # system call to finish program
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j self_loop # wait forever (not taken)
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set_timecmp: # Set timer compare to 800 ticks later
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la t0, MTIME
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la t1, MTIMECMP
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ld t0, 0(t0) # Read current timer
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addi t0, t0, 0x60 # Increment timer
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sd t0, 0(t1) # Set MTIMECMP = MTIME + 0x800
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ret
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.align 4 # trap handlers must be aligned to multiple of 4
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trap_handler:
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# Load trap handler stack pointer tp
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csrrw tp, mscratch, tp # swap MSCRATCH and tp
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sd t0, 0(tp) # Save t0 and t1 on the stack
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sd t1, -8(tp)
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csrr t0, mcause # Check the cause
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csrr t1, mtval # And the trap value
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sd t0, 0(s6) # Save MCAUSE and MTVAL in the signature
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sd t1, 8(s6)
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addi s6, s6, 16
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bgez t0, exception # if msb is clear, it is an exception
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interrupt: # must be a timer interrupt
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jal set_timecmp # Increment compare for next timer interrupt
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j trap_return # clean up and return
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exception:
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csrr t1, mepc # add 4 to MEPC to determine return Address
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addi t1, t1, 4
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csrw mepc, t1
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li t1, 8 # is it an ecall trap?
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andi t0, t0, 0xFC # if CAUSE = 8, 9, or 11
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bne t0, t1, trap_return # ignore other exceptions
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ecall:
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li t0, 4
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beq a0, t0, write_tohost # call 4: terminate program
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bltu a0, t0, changeprivilege # calls 0-3: change privilege level
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j trap_return # ignore other ecalls
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changeprivilege:
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li t0, 0x00001800 # mask off mstatus.MPP in bits 11-12
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csrc mstatus, t0
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andi a0, a0, 0x003 # only keep bottom two bits of argument
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slli a0, a0, 11 # move into mstatus.MPP position
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csrs mstatus, a0 # set mstatus.MPP with desired privilege
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trap_return: # return from trap handler
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ld t1, -8(tp) # restore t1 and t0
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ld t0, 0(tp)
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csrrw tp, mscratch, tp # restore tp
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mret # return from trap
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write_tohost:
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la t1, tohost
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li t0, 1 # 1 for success, 3 for failure
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sd t0, 0(t1) # send success code
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self_loop:
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j self_loop # wait
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.section .tohost
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tohost: # write to HTIF
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.dword 0
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fromhost:
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.dword 0
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.EQU XLEN,64
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begin_signature:
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.fill 6*(XLEN/32),4,0xdeadbeef #
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end_signature:
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# Initialize stack with room for 512 bytes
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.bss
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.space 512
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topofstack:
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# And another stack for the trap handler
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.bss
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.space 512
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topoftrapstack:
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