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cvw/fpga/constraints
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Ross Thompson 09d605ac6a Updated debug constraints again to match changes in verilog.
2022-01-08 13:28:51 -06:00
..
constraints.xdc Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
debug2.xdc Updated debug constraints again to match changes in verilog. 2022-01-08 13:28:51 -06:00