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66 lines
2.6 KiB
Systemverilog
66 lines
2.6 KiB
Systemverilog
///////////////////////////////////////////
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// subwordwrite.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 9 January 2021
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// Modified: 18 January 2023
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//
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// Purpose: Masking and muxing for subword writes
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.9)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module subwordwrite (
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input logic [2:0] LSUFunct3M,
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input logic [`LLEN-1:0] IMAFWriteDataM,
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output logic [`LLEN-1:0] LittleEndianWriteDataM
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);
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// Replicate data for subword writes
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if (`LLEN == 128) begin:sww
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always_comb
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case(LSUFunct3M[2:0])
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3'b000: LittleEndianWriteDataM = {16{IMAFWriteDataM[7:0]}}; // sb
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3'b001: LittleEndianWriteDataM = {8{IMAFWriteDataM[15:0]}}; // sh
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3'b010: LittleEndianWriteDataM = {4{IMAFWriteDataM[31:0]}}; // sw
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3'b011: LittleEndianWriteDataM = {2{IMAFWriteDataM[63:0]}}; // sd
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default: LittleEndianWriteDataM = IMAFWriteDataM; // sq
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endcase
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end else if (`LLEN == 64) begin:sww
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: LittleEndianWriteDataM = {8{IMAFWriteDataM[7:0]}}; // sb
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2'b01: LittleEndianWriteDataM = {4{IMAFWriteDataM[15:0]}}; // sh
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2'b10: LittleEndianWriteDataM = {2{IMAFWriteDataM[31:0]}}; // sw
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2'b11: LittleEndianWriteDataM = IMAFWriteDataM; // sd
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endcase
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end else begin:sww // 32-bit
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always_comb
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case(LSUFunct3M[1:0])
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2'b00: LittleEndianWriteDataM = {4{IMAFWriteDataM[7:0]}}; // sb
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2'b01: LittleEndianWriteDataM = {2{IMAFWriteDataM[15:0]}}; // sh
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2'b10: LittleEndianWriteDataM = IMAFWriteDataM; // sw
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default: LittleEndianWriteDataM = IMAFWriteDataM; // shouldn't happen
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endcase
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end
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endmodule
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