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185 lines
10 KiB
Systemverilog
185 lines
10 KiB
Systemverilog
///////////////////////////////////////////
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// decompress.sv
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//
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// Written: David_Harris@hmc.edu
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// Created: 9 January 2021
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// Modified: 18 January 2023
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//
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// Purpose: Expand 16-bit compressed instructions to 32 bits
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//
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// Documentation: RISC-V System on Chip Design Chapter 11 (Section 11.3.1)
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// RISC-V Specification 13 Dec 2019 Chapter 16 pg. 97
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// *** probably need more documentation in this file since the book is very light on decompression.
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module decompress (
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input logic [31:0] InstrRawD, // 32-bit instruction or raw compressed 16-bit instruction in bottom half
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output logic [31:0] InstrD, // Decompressed instruction
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output logic IllegalCompInstrD // Invalid decompressed instruction
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);
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logic [15:0] instr16;
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logic [4:0] rds1, rs2, rs1p, rs2p, rds1p, rdp;
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logic [11:0] immCILSP, immCILSPD, immCSS, immCSSD, immCL, immCLD, immCI, immCS, immCSD, immCB, immCIASP, immCIW;
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logic [19:0] immCJ, immCILUI;
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logic [5:0] immSH;
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logic [1:0] op;
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// Extract op and register source/destination fields
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assign instr16 = InstrRawD[15:0]; // instruction is already aligned
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assign op = instr16[1:0];
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assign rds1 = instr16[11:7];
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assign rs2 = instr16[6:2];
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assign rs1p = {2'b01, instr16[9:7]};
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assign rds1p = {2'b01, instr16[9:7]};
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assign rs2p = {2'b01, instr16[4:2]};
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assign rdp = {2'b01, instr16[4:2]};
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// extract compressed immediate formats
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assign immCILSP = {4'b0000, instr16[3:2], instr16[12], instr16[6:4], 2'b00};
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assign immCILSPD = {3'b000, instr16[4:2], instr16[12], instr16[6:5], 3'b000};
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assign immCSS = {4'b0000, instr16[8:7], instr16[12:9], 2'b00};
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assign immCSSD = {3'b000, instr16[9:7], instr16[12:10], 3'b000};
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assign immCL = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCLD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCS = {5'b0, instr16[5], instr16[12:10], instr16[6], 2'b00};
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assign immCSD = {4'b0, instr16[6:5], instr16[12:10], 3'b000};
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assign immCJ = {instr16[12], instr16[8], instr16[10:9], instr16[6], instr16[7], instr16[2], instr16[11], instr16[5:3], {9{instr16[12]}}};
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assign immCB = {{4{instr16[12]}}, instr16[6:5], instr16[2], instr16[11:10], instr16[4:3], instr16[12]};
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assign immCI = {{7{instr16[12]}}, instr16[6:2]};
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assign immCILUI = {{15{instr16[12]}}, instr16[6:2]};
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assign immCIASP = {{3{instr16[12]}}, instr16[4:3], instr16[5], instr16[2], instr16[6], 4'b0000};
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assign immCIW = {2'b00, instr16[10:7], instr16[12:11], instr16[5], instr16[6], 2'b00};
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assign immSH = {instr16[12], instr16[6:2]};
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// only for RV128
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// assign immCILSPQ = {2{instr16[5]}, instr16[5:2], instr16[12], instr16[6], 4'b0000};
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// assign immCSSQ = {2{instr16[10]}, instr16[10:7], instr16[12:11], 4'b0000};
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// assign immCLQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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// assign immCSQ = {4{instr16[10]}, instr16[6:5], instr16[12:11], 4'b0000};
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always_comb
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if (op == 2'b11) begin // noncompressed instruction
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InstrD = InstrRawD;
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IllegalCompInstrD = 0;
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end else begin // convert compressed instruction into uncompressed
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IllegalCompInstrD = 0;
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case ({op, instr16[15:13]})
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5'b00000: if (immCIW != 0) InstrD = {immCIW, 5'b00010, 3'b000, rdp, 7'b0010011}; // c.addi4spn
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else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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5'b00001: InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000111}; // c.fld
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5'b00010: InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000011}; // c.lw
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5'b00011: if (`XLEN==32)
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InstrD = {immCL, rs1p, 3'b010, rdp, 7'b0000111}; // c.flw
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else
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InstrD = {immCLD, rs1p, 3'b011, rdp, 7'b0000011}; // c.ld;
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5'b00101: InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100111}; // c.fsd
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5'b00110: InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100011}; // c.sw
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5'b00111: if (`XLEN==32)
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InstrD = {immCS[11:5], rs2p, rs1p, 3'b010, immCS[4:0], 7'b0100111}; // c.fsw
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else
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InstrD = {immCSD[11:5], rs2p, rs1p, 3'b011, immCSD[4:0], 7'b0100011}; //c.sd
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5'b01000: InstrD = {immCI, rds1, 3'b000, rds1, 7'b0010011}; // c.addi
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5'b01001: if (`XLEN==32)
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InstrD = {immCJ, 5'b00001, 7'b1101111}; // c.jal
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else
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InstrD = {immCI, rds1, 3'b000, rds1, 7'b0011011}; // c.addiw
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5'b01010: InstrD = {immCI, 5'b00000, 3'b000, rds1, 7'b0010011}; // c.li
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5'b01011: if (rds1 != 5'b00010)
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InstrD = {immCILUI, rds1, 7'b0110111}; // c.lui
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else
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InstrD = {immCIASP, rds1, 3'b000, rds1, 7'b0010011}; // c.addi16sp
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5'b01100: if (instr16[11:10] == 2'b00)
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InstrD = {6'b000000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srli
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else if (instr16[11:10] == 2'b01)
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InstrD = {6'b010000, immSH, rds1p, 3'b101, rds1p, 7'b0010011}; // c.srai
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else if (instr16[11:10] == 2'b10)
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InstrD = {immCI, rds1p, 3'b111, rds1p, 7'b0010011}; // c.andi
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else if (instr16[12:10] == 3'b011)
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0110011}; // c.sub
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b100, rds1p, 7'b0110011}; // c.xor
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else if (instr16[6:5] == 2'b10)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b110, rds1p, 7'b0110011}; // c.or
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else // if (instr16[6:5] == 2'b11)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b111, rds1p, 7'b0110011}; // c.and
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else if (`XLEN > 32) //if (instr16[12:10] == 3'b111) full truth table no need to check [12:10]
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if (instr16[6:5] == 2'b00)
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InstrD = {7'b0100000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.subw
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else if (instr16[6:5] == 2'b01)
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InstrD = {7'b0000000, rs2p, rds1p, 3'b000, rds1p, 7'b0111011}; // c.addw
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else begin // reserved
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage off
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// are excluding this branch from coverage because in rv64gc XLEN is always 64 and thus greater than 32 bits
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// This branch will only be taken if instr16[12:10] == 3'b111 and 'XLEN !> 32, because all other
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// possible values for instr16[12:10] are covered by branches above. XLEN !> 32
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// will never occur in rv64gc so this branch can not be covered
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else begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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// coverage on
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5'b01101: InstrD = {immCJ, 5'b00000, 7'b1101111}; // c.j
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5'b01110: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b000, immCB[4:0], 7'b1100011}; // c.beqz
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5'b01111: InstrD = {immCB[11:5], 5'b00000, rs1p, 3'b001, immCB[4:0], 7'b1100011}; // c.bnez
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5'b10000: InstrD = {6'b000000, immSH, rds1, 3'b001, rds1, 7'b0010011}; // c.slli
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5'b10001: InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000111}; // c.fldsp
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5'b10010: InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000011}; // c.lwsp
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5'b10011: if (`XLEN == 32)
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InstrD = {immCILSP, 5'b00010, 3'b010, rds1, 7'b0000111}; // c.flwsp
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else
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InstrD = {immCILSPD, 5'b00010, 3'b011, rds1, 7'b0000011}; // c.ldsp
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5'b10100: if (instr16[12] == 0)
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if (instr16[6:2] == 5'b00000)
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InstrD = {7'b0000000, 5'b00000, rds1, 3'b000, 5'b00000, 7'b1100111}; // c.jr
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else
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InstrD = {7'b0000000, rs2, 5'b00000, 3'b000, rds1, 7'b0110011}; // c.mv
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else
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if (rs2 == 5'b00000)
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if (rds1 == 5'b00000)
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InstrD = {12'b1, 5'b00000, 3'b000, 5'b00000, 7'b1110011}; // c.ebreak
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else
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InstrD = {12'b0, rds1, 3'b000, 5'b00001, 7'b1100111}; // c.jalr
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else
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InstrD = {7'b0000000, rs2, rds1, 3'b000, rds1, 7'b0110011}; // c.add
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5'b10101: InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100111}; // c.fsdsp
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5'b10110: InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100011}; // c.swsp
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5'b10111: if (`XLEN==32)
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InstrD = {immCSS[11:5], rs2, 5'b00010, 3'b010, immCSS[4:0], 7'b0100111}; // c.fswsp
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else
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InstrD = {immCSSD[11:5], rs2, 5'b00010, 3'b011, immCSSD[4:0], 7'b0100011}; // c.sdsp
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default: begin // illegal instruction
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IllegalCompInstrD = 1;
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InstrD = {16'b0, instr16}; // preserve instruction for mtval on trap
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end
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endcase
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end
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endmodule
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