Diego Herrera Vicioso 16fd17be39 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc		2023-04-15 23:13:39 -07:00
..
csr.sv	Coverage improvements in ieu, hazard units	2023-03-31 08:33:46 -07:00
csrc.sv	Excluded coverage for misaligned instructions	2023-04-10 23:18:25 -07:00
csri.sv	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
csrm.sv	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
csrs.sv	Refactored InstrValidNotFlushed into CSR Write signals	2023-03-30 17:06:09 -07:00
csrsr.sv	Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc	2023-04-15 23:13:39 -07:00
csru.sv	Started factoring out InstrValidNotFlushed from CSRs	2023-03-30 14:56:19 -07:00
privdec.sv	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
privileged.sv	Merge branch 'main' of https://github.com/openhwgroup/cvw	2023-04-05 14:55:12 -05:00
privmode.sv	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
privpiperegs.sv	Progress on bug 203.	2023-04-05 13:20:04 -05:00
trap.sv	Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc	2023-04-15 23:13:39 -07:00