Ross Thompson 0cc47f3daf Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.		2021-08-23 15:46:17 -05:00
..
csr.sv	Wally previously was overcounting retired instructions when they were flushed.	2021-08-23 12:24:03 -05:00
csrc.sv	Wally previously was overcounting retired instructions when they were flushed.	2021-08-23 12:24:03 -05:00
csri.sv	Confirmed David's changes to the interrupt code.	2021-08-22 21:36:31 -05:00
csrm.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrn.sv	Gave names to for loops in generate blocks for ease of reference	2021-07-04 18:52:16 -04:00
csrs.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csrsr.sv	fixed the read timer issue but we still have problems with interrupts and i/o devices.	2021-08-06 10:16:06 -05:00
csru.sv	Fixed writting MStatus FS bits	2021-07-13 13:20:30 -04:00
privdec.sv	Implemented TSR, TW, TVM, MXR status bits	2021-07-06 01:32:05 -04:00
privileged.sv	Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.	2021-08-23 15:46:17 -05:00
trap.sv	Switched ExceptionM to dcache to be just exceptions.	2021-08-13 15:53:50 -05:00