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118 lines
4.7 KiB
Systemverilog
118 lines
4.7 KiB
Systemverilog
///////////////////////////////////////////
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// ieu.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Integer Execution Unit: datapath and controller
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//
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// Documentation: RISC-V System on Chip Design Chapter 4 (Figure 4.12)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module ieu (
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input logic clk, reset,
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// Decode Stage interface
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input logic [31:0] InstrD,
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input logic IllegalIEUInstrFaultD,
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output logic IllegalBaseInstrFaultD,
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// Execute Stage interface
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input logic [`XLEN-1:0] PCE,
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input logic [`XLEN-1:0] PCLinkE,
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input logic FWriteIntE, FCvtIntE, FCvtIntW,
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output logic [`XLEN-1:0] IEUAdrE,
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output logic IntDivE, W64E,
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output logic [2:0] Funct3E,
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output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // these are the src outputs before the mux choosing between them and PCE to put in srcA/B
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// Memory stage interface
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input logic SquashSCW, // from LSU
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output logic [1:0] MemRWM, // read/write control goes to LSU
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output logic [1:0] AtomicM, // atomic control goes to LSU
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output logic [`XLEN-1:0] WriteDataM, // write data to LSU
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output logic [2:0] Funct3M, // size and signedness to LSU
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output logic [`XLEN-1:0] SrcAM, // to privilege and fpu
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output logic [4:0] RdE, RdM,
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input logic [`XLEN-1:0] FIntResM,
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output logic InvalidateICacheM, FlushDCacheM,
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// Writeback stage
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input logic [`XLEN-1:0] FIntDivResultW,
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input logic [`XLEN-1:0] CSRReadValW, MDUResultW,
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input logic [`XLEN-1:0] FCvtIntResW,
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output logic [4:0] RdW,
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input logic [`XLEN-1:0] ReadDataW,
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output logic InstrValidM,
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// hazards
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input logic StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic FCvtIntStallD, LoadStallD, MDUStallD, CSRRdStallD,
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output logic PCSrcE,
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output logic CSRReadM, CSRWriteM, PrivilegedM,
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output logic CSRWriteFenceM,
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output logic StoreStallD
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);
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logic [2:0] ImmSrcD;
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logic [1:0] FlagsE;
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logic [2:0] ALUControlE;
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logic ALUSrcAE, ALUSrcBE;
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logic [2:0] ResultSrcW;
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logic ALUResultSrcE;
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logic SCE;
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logic FWriteIntM;
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logic IntDivW;
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// forwarding signals
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logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E;
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logic [1:0] ForwardAE, ForwardBE;
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logic RegWriteM, RegWriteW;
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logic MemReadE, CSRReadE;
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logic JumpE;
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logic BranchSignedE;
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logic MDUE;
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controller c(
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.clk, .reset, .StallD, .FlushD, .InstrD, .ImmSrcD,
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.IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD, .StallE, .FlushE, .FlagsE, .FWriteIntE,
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.PCSrcE, .ALUControlE, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .MemReadE, .CSRReadE,
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.Funct3E, .IntDivE, .MDUE, .W64E, .JumpE, .SCE, .BranchSignedE, .StallM, .FlushM, .MemRWM,
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.CSRReadM, .CSRWriteM, .PrivilegedM, .AtomicM, .Funct3M,
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.RegWriteM, .InvalidateICacheM, .FlushDCacheM, .InstrValidM, .FWriteIntM,
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.StallW, .FlushW, .RegWriteW, .IntDivW, .ResultSrcW, .CSRWriteFenceM, .StoreStallD);
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datapath dp(
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.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
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.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE,
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.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
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.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
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.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
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.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
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forward fw(
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.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
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.MemReadE, .MDUE, .CSRReadE, .RegWriteM, .RegWriteW,
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.FCvtIntE, .SCE, .ForwardAE, .ForwardBE,
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.FCvtIntStallD, .LoadStallD, .MDUStallD, .CSRRdStallD);
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endmodule
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