mirror of
https://github.com/openhwgroup/cvw
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115 lines
4.4 KiB
Systemverilog
115 lines
4.4 KiB
Systemverilog
///////////////////////////////////////////
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// gshare.sv
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//
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// Written: Ross Thompson
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// Email: ross1728@gmail.com
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// Created: 16 March 2021
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// Adapted from ssanghai@hmc.edu (Shreya Sanghai)
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// Modified: 20 February 2023
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//
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// Purpose: gshare and Global History Branch predictors
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module gshare #(parameter k = 10,
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parameter integer TYPE = 1) (
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input logic clk,
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input logic reset,
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input logic StallF, StallD, StallE, StallM, StallW,
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input logic FlushD, FlushE, FlushM, FlushW,
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output logic [1:0] BPDirPredF,
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output logic BPDirPredWrongE,
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// update
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input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
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input logic BPBranchF, BranchD, BranchE, BranchM, BranchW, PCSrcE
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);
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logic MatchF, MatchD, MatchE, MatchM, MatchW;
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logic MatchX;
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logic [1:0] TableBPDirPredF, BPDirPredD, BPDirPredE, FwdNewDirPredF;
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logic [1:0] NewBPDirPredE, NewBPDirPredM, NewBPDirPredW;
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logic [k-1:0] IndexNextF, IndexF, IndexD, IndexE, IndexM, IndexW;
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logic [k-1:0] GHRF, GHRD, GHRE, GHRM;
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logic [k-1:0] GHRNextM, GHRNextF;
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logic PCSrcM;
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if(TYPE == 1) begin
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assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
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assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
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assign IndexD = GHRD ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
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assign IndexE = GHRE ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
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assign IndexM = GHRM ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
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end else if(TYPE == 0) begin
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assign IndexNextF = GHRNextF;
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assign IndexF = GHRF;
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assign IndexD = GHRD;
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assign IndexE = GHRE;
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assign IndexM = GHRM;
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end
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flopenrc #(k) IndexWReg(clk, reset, FlushW, ~StallW, IndexM, IndexW);
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assign MatchD = BranchD & ~FlushE & (IndexF == IndexD);
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assign MatchE = BranchE & ~FlushM & (IndexF == IndexE);
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assign MatchM = BranchM & ~FlushW & (IndexF == IndexM);
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assign MatchW = BranchW & ~FlushW & (IndexF == IndexW);
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assign MatchX = MatchD | MatchE | MatchM | MatchW;
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assign FwdNewDirPredF = MatchD ? {2{BPDirPredD[1]}} :
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MatchE ? {NewBPDirPredE} :
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MatchM ? {NewBPDirPredM} :
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NewBPDirPredW ;
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assign BPDirPredF = MatchX ? FwdNewDirPredF : TableBPDirPredF;
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ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
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.ce1(~StallF), .ce2(~StallW & ~FlushW),
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.ra1(IndexNextF),
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.rd1(TableBPDirPredF),
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.wa2(IndexM),
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.wd2(NewBPDirPredM),
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.we2(BranchM),
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.bwe2(1'b1));
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flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, BPDirPredF, BPDirPredD);
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flopenrc #(2) PredictionRegE(clk, reset, FlushE, ~StallE, BPDirPredD, BPDirPredE);
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satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(BPDirPredE), .NewState(NewBPDirPredE));
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flopenrc #(2) NewPredictionRegM(clk, reset, FlushM, ~StallM, NewBPDirPredE, NewBPDirPredM);
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flopenrc #(2) NewPredictionRegW(clk, reset, FlushW, ~StallW, NewBPDirPredM, NewBPDirPredW);
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assign BPDirPredWrongE = PCSrcE != BPDirPredE[1] & BranchE;
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assign GHRNextF = BPBranchF ? {BPDirPredF[1], GHRF[k-1:1]} : GHRF;
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assign GHRF = BranchD ? {BPDirPredD[1], GHRD[k-1:1]} : GHRD;
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assign GHRD = BranchE ? {PCSrcE, GHRE[k-1:1]} : GHRE;
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assign GHRE = BranchM ? {PCSrcM, GHRM[k-1:1]} : GHRM;
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assign GHRNextM = {PCSrcM, GHRM[k-1:1]};
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flopenr #(k) GHRReg(clk, reset, ~StallW & ~FlushW & BranchM, GHRNextM, GHRM);
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flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
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endmodule
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