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https://github.com/openhwgroup/cvw
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53 lines
1.6 KiB
Systemverilog
53 lines
1.6 KiB
Systemverilog
///////////////////////////////////////////
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// rconlut32.sv
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//
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// Written: ryan.swann@okstate.edu, james.stine@okstate.edu
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// Created: 20 February 2024
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//
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// Purpose: rcon lookup for aes64ks1i instruction
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-24 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module rconlut32(
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input logic [3:0] rd,
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output logic [31:0] rcon
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);
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logic [7:0] rcon8;
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always_comb
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case(rd)
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4'h0 : rcon8 = 8'h01;
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4'h1 : rcon8 = 8'h02;
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4'h2 : rcon8 = 8'h04;
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4'h3 : rcon8 = 8'h08;
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4'h4 : rcon8 = 8'h10;
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4'h5 : rcon8 = 8'h20;
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4'h6 : rcon8 = 8'h40;
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4'h7 : rcon8 = 8'h80;
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4'h8 : rcon8 = 8'h1b;
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4'h9 : rcon8 = 8'h36;
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4'hA : rcon8 = 8'h00;
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default : rcon8 = 8'h00;
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endcase
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assign rcon = {24'b0, rcon8};
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endmodule
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