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287 lines
14 KiB
Systemverilog
Executable File
287 lines
14 KiB
Systemverilog
Executable File
///////////////////////////////////////////
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//
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// Written: James.Stine@okstate.edu 1 February 2021
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// Modified:
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//
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// Purpose: FP Add/Sub instructions
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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//
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// Basic and Denormalized Operations
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//
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// Step 1: Load operands, set flags, and convert SP to DP
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// Step 2: Check for special inputs ( +/- Infinity, NaN)
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// Step 3: Compare exponents. Swap the operands of exp1 < exp2
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// or of (exp1 = exp2 AND mnt1 < mnt2)
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// Step 4: Shift the mantissa corresponding to the smaller exponent,
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// and extend precision by three bits to the right.
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// Step 5: Add or subtract the mantissas.
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// Step 6: Normalize the result.//
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// Shift left until normalized. Normalized when the value to the
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// left of the binrary point is 1.
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// Step 7: Round the result.//
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// Step 8: Put sum onto output.
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//
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module fpadd (AS_Result, Flags, Denorm, op1, op2, rm, op_type, P, OvEn, UnEn);
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input [63:0] op1; // 1st input operand (A)
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input [63:0] op2; // 2nd input operand (B)
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input [2:0] rm; // Rounding mode - specify values
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input [3:0] op_type; // Function opcode
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input P; // Result Precision (0 for double, 1 for single)
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input OvEn; // Overflow trap enabled
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input UnEn; // Underflow trap enabled
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output [63:0] AS_Result; // Result of operation
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output [4:0] Flags; // IEEE exception flags
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output Denorm; // Denorm on input or output
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wire [63:0] Float1;
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wire [63:0] Float2;
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wire [63:0] IntValue;
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wire [11:0] exp1, exp2;
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wire [11:0] exp_diff1, exp_diff2;
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wire [10:0] exponent, exp_pre;
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wire [11:0] exp_shift;
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wire [63:0] Result;
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wire [51:0] mantissaA;
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wire [56:0] mantissaA1;
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wire [63:0] mantissaA3;
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wire [51:0] mantissaB;
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wire [56:0] mantissaB1, mantissaB2;
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wire [63:0] mantissaB3;
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wire [63:0] sum, sum_tc, sum_corr, sum_norm, sum_norm_w_bypass;
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wire [5:0] align_shift;
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wire [5:0] norm_shift, norm_shift_denorm;
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wire [3:0] sel_inv;
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wire op1_Norm, op2_Norm;
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wire opA_Norm, opB_Norm;
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wire Invalid;
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wire DenormIn, DenormIO;
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wire [4:0] FlagsIn;
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wire exp_valid;
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wire exp_gt63;
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wire Sticky_out;
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wire signA, sign_corr;
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wire corr_sign;
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wire zeroB;
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wire convert;
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wire swap;
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wire sub;
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wire [10:0] exponent_postsum;
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wire mantissa_comp;
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wire mantissa_comp_sum;
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wire mantissa_comp_sum_tc;
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wire Float1_sum_comp;
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wire Float2_sum_comp;
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wire Float1_sum_tc_comp;
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wire Float2_sum_tc_comp;
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wire [5:0] ZP_mantissaA;
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wire [5:0] ZP_mantissaB;
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wire ZV_mantissaA;
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wire ZV_mantissaB;
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wire normal_underflow;
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wire normal_overflow;
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// Convert the input operands to their appropriate forms based on
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// the orignal operands, the op_type , and their precision P.
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// Single precision inputs are converted to double precision
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// and the sign of the first operand is set appropratiately based on
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// if the operation is absolute value or negation.
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convert_inputs conv1 (Float1, Float2, op1, op2, op_type, P);
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// Test for exceptions and return the "Invalid Operation" and
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// "Denormalized" Input Flags. The "sel_inv" is used in
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// the third pipeline stage to select the result. Also, op1_Norm
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// and op2_Norm are one if op1 and op2 are not zero or denormalized.
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// sub is one if the effective operation is subtaction.
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exception exc1 (sel_inv, Invalid, DenormIn, op1_Norm, op2_Norm, sub,
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Float1, Float2, op_type);
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// Perform Exponent Subtraction (used for alignment). For performance
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// both exponent subtractions are performed in parallel. This was
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// changed to a behavior level to allow the tools to try to optimize
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// the two parallel additions. The input values are zero-extended to 12
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// bits prior to performing the addition.
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assign exp1 = {1'b0, Float1[62:52]};
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assign exp2 = {1'b0, Float2[62:52]};
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assign exp_diff1 = exp1 - exp2;
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assign exp_diff2 = DenormIn ? ({Float2[63], exp2[10:0]} - {Float1[63], exp1[10:0]}): exp2 - exp1;
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// The second operand (B) should be set to zero, if op_type does not
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// specify addition or subtraction
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assign zeroB = op_type[2] | op_type[1];
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// Swapped operands if zeroB is not one and exp1 < exp2.
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// Swapping causes exp2 to be used for the result exponent.
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// Only the exponent of the larger operand is used to determine
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// the final result.
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assign swap = exp_diff1[11] & ~zeroB;
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assign exponent = swap ? exp2[10:0] : exp1[10:0];
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assign exponent_postsum = swap ? exp2[10:0] : exp1[10:0];
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assign mantissaA = swap ? Float2[51:0] : Float1[51:0];
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assign mantissaB = swap ? Float1[51:0] : Float2[51:0];
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assign signA = swap ? Float2[63] : Float1[63];
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// Leading-Zero Detector. Determine the size of the shift needed for
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// normalization. If sum_corrected is all zeros, the exp_valid is
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// zero; otherwise, it is one.
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// modified to 52 bits to detect leading zeroes on denormalized mantissas
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lz52 lz_norm_1 (ZP_mantissaA, ZV_mantissaA, mantissaA);
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lz52 lz_norm_2 (ZP_mantissaB, ZV_mantissaB, mantissaB);
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// Denormalized exponents created by subtracting the leading zeroes from the original exponents
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assign exp1_denorm = swap ? (exp1 - ZP_mantissaB) : (exp1 - ZP_mantissaA);
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assign exp2_denorm = swap ? (exp2 - ZP_mantissaA) : (exp2 - ZP_mantissaB);
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// Finds normal underflow result to determine whether to round final exponent down
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// Comparison between each float and the resulting sum of the primary cla adder/subtractor and cla subtractor
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assign Float1_sum_comp = (Float1[51:0] > sum[51:0]) ? 1'b0 : 1'b1;
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assign Float2_sum_comp = (Float2[51:0] > sum[51:0]) ? 1'b0 : 1'b1;
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assign Float1_sum_tc_comp = (Float1[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1;
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assign Float2_sum_tc_comp = (Float2[51:0] > sum_tc[51:0]) ? 1'b0 : 1'b1;
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// Determines the correct Float value to compare based on swap result
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assign mantissa_comp_sum = swap ? Float2_sum_comp : Float1_sum_comp;
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assign mantissa_comp_sum_tc = swap ? Float2_sum_tc_comp : Float1_sum_tc_comp;
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// Determines the correct comparison result based on operation and sign of resulting sum
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assign mantissa_comp = (op_type[0] ^ sum[63]) ? mantissa_comp_sum_tc : mantissa_comp_sum;
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// If the signs are different and both operands aren't denormalized
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// the normal underflow bit is needed and therefore updated.
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assign normal_underflow = ((Float1[63] ~^ Float2[63]) & (opA_Norm | opB_Norm)) ? mantissa_comp : 1'b0;
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// Determine the alignment shift and limit it to 63. If any bit from
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// exp_shift[6] to exp_shift[11] is one, then shift is set to all ones.
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assign exp_shift = swap ? exp_diff2 : exp_diff1;
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assign exp_gt63 = exp_shift[11] | exp_shift[10] | exp_shift[9]
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| exp_shift[8] | exp_shift[7] | exp_shift[6];
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assign align_shift = exp_shift | {6{exp_gt63}};
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// Unpack the 52-bit mantissas to 57-bit numbers of the form.
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// 001.M[51]M[50] ... M[1]M[0]00
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// Unless the number has an exponent of zero, in which case it
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// is unpacked as
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// 000.00 ... 00
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// This effectively flushes denormalized values to zero.
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// The three bits of to the left of the binary point prevent overflow
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// and loss of sign information. The two bits to the right of the
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// original mantissa form the "guard" and "round" bits that are used
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// to round the result.
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assign opA_Norm = swap ? op2_Norm : op1_Norm;
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assign opB_Norm = swap ? op1_Norm : op2_Norm;
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assign mantissaA1 = {2'h0, opA_Norm, mantissaA[51:0]&{52{opA_Norm}}, 2'h0};
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assign mantissaB1 = {2'h0, opB_Norm, mantissaB[51:0]&{52{opB_Norm}}, 2'h0};
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// Perform mantissa alignment using a 57-bit barrel shifter
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// If any of the bits shifted out are one, Sticky_out is set.
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// The size of the barrel shifter could be reduced by two bits
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// by not adding the leading two zeros until after the shift.
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barrel_shifter_r57 bs1 (mantissaB2, Sticky_out, mantissaB1, align_shift);
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// Place either the sign-extened 32-bit value or the original 64-bit value
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// into IntValue (to be used for integer to floating point conversion)
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assign IntValue [31:0] = op1[31:0];
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assign IntValue [63:32] = op_type[0] ? {32{op1[31]}} : op1[63:32];
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// If doing an integer to floating point conversion, mantissaA3 is set to
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// IntVal and the prenomalized exponent is set to 1084. Otherwise,
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// mantissaA3 is simply extended to 64-bits by setting the 7 LSBs to zero,
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// and the exponent value is left unchanged.
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// Under denormalized cases, the exponent before the rounder is set to 1
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// if the normal shift value is 11.
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assign convert = ~op_type[2] & op_type[1];
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assign mantissaA3 = (op_type[3]) ? (op_type[0] ? Float1 : ~Float1) : (DenormIn ? ({12'h0, mantissaA}) : (convert ? IntValue : {mantissaA1, 7'h0}));
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assign exp_pre = DenormIn ?
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((norm_shift == 6'b001011) ? 11'b00000000001 : (swap ? exp2_denorm : exp1_denorm))
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: (convert ? 11'b10000111100 : exponent);
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// Put zero in for mantissaB3, if zeroB is one. Otherwise, B is extended to
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// 64-bits by setting the 7 LSBs to the Sticky_out bit followed by six
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// zeros.
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assign mantissaB3[63:7] = (op_type[3]) ? (57'h0) : (DenormIn ? {12'h0, mantissaB[51:7]} : mantissaB2 & {57{~zeroB}});
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assign mantissaB3[6] = (op_type[3]) ? (1'b0) : (DenormIn ? mantissaB[6] : Sticky_out & ~zeroB);
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assign mantissaB3[5:0] = (op_type[3]) ? (6'h01) : (DenormIn ? mantissaB[5:0] : 6'h0);
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// The sign of the result needs to be corrected if the true
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// operation is subtraction and the input operands were swapped.
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assign corr_sign = ~op_type[2]&~op_type[1]&op_type[0]&swap;
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// 64-bit Mantissa Adder/Subtractor
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cla64 add1 (sum, mantissaA3, mantissaB3, sub); //***adder
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// 64-bit Mantissa Subtractor - to get the two's complement of the
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// result when the sign from the adder/subtractor is negative.
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cla_sub64 sub1 (sum_tc, mantissaB3, mantissaA3); //***adder
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// Determine the correct sign of the result
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assign sign_corr = ((corr_sign ^ signA) & ~convert) ^ sum[63];
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// If the sum is negative, use its two complement instead.
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// This value has to be 64-bits to correctly handle the
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// case 10...00
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assign sum_corr = (DenormIn & (opA_Norm | opB_Norm) & ( ( (Float1[63] ~^ Float2[63]) & op_type[0] ) | ((Float1[63] ^ Float2[63]) & ~op_type[0]) ))
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? (sum[63] ? sum : sum_tc) : ( (op_type[3]) ? sum : (sum[63] ? sum_tc : sum));
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// Finds normal underflow result to determine whether to round final exponent down
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assign normal_overflow = (DenormIn & (sum == 16'h0) & (opA_Norm | opB_Norm) & ~op_type[0]) ? 1'b1 : (sum[63] ? sum_tc[52] : sum[52]);
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// Leading-Zero Detector. Determine the size of the shift needed for
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// normalization. If sum_corrected is all zeros, the exp_valid is
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// zero; otherwise, it is one.
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lz64 lzd1 (norm_shift, exp_valid, sum_corr);
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assign norm_shift_denorm = (DenormIn & ( (~opA_Norm & ~opB_Norm) | normal_underflow)) ? (6'h00) : (norm_shift);
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// Barell shifter used for normalization. It takes as inputs the
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// the corrected sum and the amount by which the sum should
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// be right shifted. It outputs the normalized sum.
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barrel_shifter_l64 bs2 (sum_norm, sum_corr, norm_shift_denorm);
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assign sum_norm_w_bypass = (op_type[3]) ? (op_type[0] ? ~sum_corr : sum_corr) : (sum_norm);
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// Round the mantissa to a 52-bit value, with the leading one
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// removed. If the result is a single precision number, the actual
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// mantissa is in the upper 23 bits and the lower 29 bits are zero.
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// At this point, normalization has already been performed, so we know
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// exactly where the rounding point is. The rounding units also
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// handles special cases and set the exception flags.
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// Changed DenormIO -> Denorm and FlagsIn -> Flags in order to
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// help in processor reservation station detection of load/stores. In
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// other words, the processor would like to know ahead of time that
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// if the result is an exception then don't load or store.
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rounder round1 (Result, DenormIO, FlagsIn, rm, P, OvEn, UnEn, exp_valid,
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sel_inv, Invalid, DenormIn, convert, sign_corr, exp_pre, norm_shift, sum_norm_w_bypass,
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exponent_postsum, op1_Norm, op2_Norm, Float1[63:52], Float2[63:52],
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normal_overflow, normal_underflow, swap, op_type, sum);
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// Store the final result and the exception flags in registers.
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assign AS_Result = Result;
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assign {Denorm, Flags} = {DenormIO, FlagsIn};
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endmodule // fpadd
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