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This test basically triggers an i$ miss during a d$ (hit) store operation. It requires some tricky timing (e.g. a flushD right before the relevant store). I use a script to generate the test.
87 lines
3.3 KiB
Python
87 lines
3.3 KiB
Python
####################
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# dcache1.py
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#
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# Written: avercruysse@hmc.edu 18 April 2023
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#
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# Purpose: Test Coverage for D$
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# (For each way, trigger a CacheDataMem write enable while chip enable is low)
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#
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# A component of the CORE-V-WALLY configurable RISC-V project.
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#
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# Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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#
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# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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#
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# Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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# except in compliance with the License, or, at your option, the Apache License version 2.0. You
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# may obtain a copy of the License at
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#
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# https://solderpad.org/licenses/SHL-2.1/
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#
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# Unless required by applicable law or agreed to in writing, any work distributed under the
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# License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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# either express or implied. See the License for the specific language governing permissions
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# and limitations under the License.
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################################################
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import os
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test_name = "dcache1.S"
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dcache_num_ways = 4
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dcache_way_size_in_bytes = 4096
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# warning i$ line size is not currently parameterized.
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# arbitrary start location of where I send stores to.
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mem_start_addr = 0x80100000
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# pointer to the start of unused memory (strictly increasing)
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mem_addr = mem_start_addr
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def wl(line="", comment=None, fname=test_name):
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with open(fname, "a") as f:
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instr = False if (":" in line or
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".align" in line or
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"# include" in line) else True
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indent = 6 if instr else 0
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comment = "// " + comment if comment is not None else ""
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to_write = " " * indent + line + comment + "\n"
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f.write(to_write)
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def write_repro_instrs():
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"""
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Assumes that the store location has been fetched to d$, and is in t0.
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"""
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for i in range(16): # write a whole cache set.
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if i == 12:
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wl('sd zero, 0(t0)') # D$ write to set PCM = PCF + 8 for proper alignment (stallD will happen).
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elif i == 13:
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# the store in question happens here, at adresses 0x34, 0x74
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wl('sd zero, 0(t0)') # it should hit this time
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else:
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# can't be a NOP or anything else that is encoded as compressed.
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# this is because the branch predictor will use the wrong address
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# so the IFU cache miss will come late.
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wl('.word 0x00000013') # addi x0, x0, 0 (canonical NOP, uncompressed).
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if __name__ == "__main__":
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if os.path.exists(test_name):
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os.remove(test_name)
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# os.rename(test_name, test_name + ".old")
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wl(comment="This file is generated by dcache1.py (run that script manually)")
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wl('#include "WALLY-init-lib.h"')
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wl('main:')
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# excercise all 4 D$ ways. If they're not all full, it uses the first empty.
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# So we are sure all 4 ways are exercised.
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for i in range(dcache_num_ways):
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wl(comment=f"start way test #{i+1}")
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wl(f'li t0, {hex(mem_addr)}')
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wl(f'.align 6') # start at i$ set boundary. 6 lsb bits are zero.
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wl(comment=f"i$ boundary, way test #{i+1}")
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write_repro_instrs()
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mem_addr += dcache_way_size_in_bytes # so that we excercise a new D$ way.
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wl("j done")
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