Ross Thompson dd9fe60b28 Write of the SDC address register is correct. The command register is not yet working. ... The root problem is the command register needs to be reset at the end of the SDC transaction.		2021-09-24 18:48:11 -05:00
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bin	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
config	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
fpu-testfloat/FMA/tbgen	FMA cleanup	2021-08-28 10:53:35 -04:00
linux-testgen	created script to determine which functions are most frequently used	2021-09-14 19:41:05 -04:00
misc	Clean up MMU code	2021-05-14 07:12:32 -04:00
ppa	Config file for ppa experiments	2021-03-25 10:23:21 -05:00
regression	Write of the SDC address register is correct. The command register is not yet working.	2021-09-24 18:48:11 -05:00
src	Write of the SDC address register is correct. The command register is not yet working.	2021-09-24 18:48:11 -05:00
testbench	Have program which checks for sdc init and issues read, but read done is	2021-09-24 15:53:38 -05:00
testgen	mcause test fixes and s-mode interrupt bugfix	2021-06-16 17:37:08 -04:00
lint-wally	Merge difficulties	2021-06-07 09:50:23 -04:00
proposed-sdc.txt	Initial SD Card reader.	2021-09-22 10:50:29 -05:00