Ross Thompson 4322694f7a Switch to use RV64IC for the benchmarks. ... Still not working correctly with the icache. instr addr correct got		2021-04-07 19:12:43 -05:00
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function_radix.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
testbench-busybear.sv	Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.	2021-03-30 23:18:20 -05:00
testbench-coremark_bare.sv	removed minor bugs	2021-03-25 20:29:50 -04:00
testbench-coremark.sv	removed minor bugs	2021-03-25 20:29:50 -04:00
testbench-imperas.sv	Switch to use RV64IC for the benchmarks.	2021-04-07 19:12:43 -05:00
testbench-peripherals.sv	removed minor bugs	2021-03-25 20:29:50 -04:00
testbench-privileged.sv	Merge branch 'PPA' into main	2021-03-25 20:35:21 -04:00