mirror of
https://github.com/openhwgroup/cvw
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42ef1e22e5
2. Removed the write address delay from simpleram.sv 3. Fixed rv32tim and rv32ic mode to handle missalignment correctly. 4. Added imperas32i and imperas32c to rv32tim mode. |
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| .. | ||
| flop.sv | ||
| flopen.sv | ||
| flopenl.sv | ||
| flopenr.sv | ||
| flopenrc.sv | ||
| flopens.sv | ||
| flopr.sv | ||
| floprc.sv | ||
| simpleram.sv | ||
| synchronizer.sv | ||