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42c0a10d07
FlushW prevents writting the cache, dtim, and bus state. FlushW still gates HTRANS. FlushW does not impact the mealy outputs of the cache and bus FSMs and hazard is updated to not stall W if we get a trap.
95 lines
5.2 KiB
Systemverilog
95 lines
5.2 KiB
Systemverilog
///////////////////////////////////////////
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// hazard.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Determine forwarding, stalls and flushes
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// MIT LICENSE
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this
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// software and associated documentation files (the "Software"), to deal in the Software
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// without restriction, including without limitation the rights to use, copy, modify, merge,
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// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
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// to whom the Software is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or
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// substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
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// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
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// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
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// OR OTHER DEALINGS IN THE SOFTWARE.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module hazard(
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// Detect hazards
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(* mark_debug = "true" *) input logic BPPredWrongE, CSRWriteFencePendingDEM, RetM, TrapM,
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(* mark_debug = "true" *) input logic LoadStallD, StoreStallD, MDUStallD, CSRRdStallD,
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(* mark_debug = "true" *) input logic LSUStallM, IFUStallF,
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(* mark_debug = "true" *) input logic FPUStallD, FStallD,
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(* mark_debug = "true" *) input logic DivBusyE,FDivBusyE,
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(* mark_debug = "true" *) input logic EcallFaultM, BreakpointFaultM,
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(* mark_debug = "true" *) input logic wfiM, IntPendingM,
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// Stall & flush outputs
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(* mark_debug = "true" *) output logic StallF, StallD, StallE, StallM, StallW,
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(* mark_debug = "true" *) output logic FlushF, FlushD, FlushE, FlushM, FlushW
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);
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logic StallFCause, StallDCause, StallECause, StallMCause, StallWCause;
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logic FirstUnstalledD, FirstUnstalledE, FirstUnstalledM, FirstUnstalledW;
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// stalls and flushes
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// loads: stall for one cycle if the subsequent instruction depends on the load
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// branches and jumps: flush the next two instructions if the branch is taken in EXE
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// CSR Writes: stall all instructions after the CSR until it completes, except that PC must change when branch is resolved
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// this also applies to other privileged instructions such as M/S/URET, ECALL/EBREAK
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// Exceptions: flush entire pipeline
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// Ret instructions: occur in M stage. Might be possible to move earlier, but be careful about hazards
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// General stall and flush rules:
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// A stage must stall if the next stage is stalled
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// If any stages are stalled, the first stage that isn't stalled must flush.
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// *** can stalls be pushed into earlier stages (e.g. no stall after Decode?)
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// *** consider replacing CSRWriteFencePendingDEM with a flush rather than a stall.
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assign StallFCause = CSRWriteFencePendingDEM & ~(TrapM | RetM | BPPredWrongE);
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// stall in decode if instruction is a load/mul/csr dependent on previous
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assign StallDCause = (LoadStallD | StoreStallD | MDUStallD | CSRRdStallD | FPUStallD | FStallD) & ~(TrapM | RetM | BPPredWrongE);
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// assign StallECause = (DivBusyE | FDivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
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assign StallECause = (DivBusyE) & ~(TrapM); // *** can we move to decode stage (KP?)
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// WFI terminates if any enabled interrupt is pending, even if global interrupts are disabled. It could also terminate with TW trap
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// assign StallMCause = (wfiM & (~TrapM & ~IntPendingM)); // | FDivBusyE;
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assign StallMCause = ((wfiM) & (~TrapM & ~IntPendingM)); //*** Ross: should FDivBusyE trigger StallECause rather than StallMCause similar to DivBusyE?
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assign StallWCause = ((IFUStallF | LSUStallM) & ~TrapM) | (FDivBusyE & ~TrapM & ~IntPendingM);
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assign #1 StallF = StallFCause | StallD;
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assign #1 StallD = StallDCause | StallE;
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assign #1 StallE = StallECause | StallM;
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assign #1 StallM = StallMCause | StallW;
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assign #1 StallW = StallWCause;
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assign FirstUnstalledD = ~StallD & StallF;
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assign FirstUnstalledE = ~StallE & StallD;
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assign FirstUnstalledM = ~StallM & StallE;
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assign FirstUnstalledW = ~StallW & StallM;
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// Each stage flushes if the previous stage is the last one stalled (for cause) or the system has reason to flush
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assign #1 FlushF = BPPredWrongE;
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assign #1 FlushD = FirstUnstalledD | TrapM | RetM | BPPredWrongE;
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assign #1 FlushE = FirstUnstalledE | TrapM | RetM | BPPredWrongE; // *** why is BPPredWrongE here, but not needed in simple processor
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assign #1 FlushM = FirstUnstalledM | TrapM | RetM;
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// on Trap the memory stage should be flushed going into the W stage,
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// except if the instruction causing the Trap is an ecall or ebreak.
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assign #1 FlushW = FirstUnstalledW | (TrapM & ~(BreakpointFaultM | EcallFaultM));
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endmodule
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