mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
90 lines
2.0 KiB
Plaintext
90 lines
2.0 KiB
Plaintext
/dts-v1/;
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/ {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "wally-virt";
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model = "wally-virt,qemu";
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chosen {
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linux,initrd-end = <0x85c43a00>;
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linux,initrd-start = <0x84200000>;
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bootargs = "root=/dev/vda ro console=ttyS0,115200";
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stdout-path = "/soc/uart@10000000";
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x00 0x80000000 0x00 0x10000000>;
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};
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cpus {
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#address-cells = <0x01>;
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#size-cells = <0x00>;
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clock-frequency = <0x43B5FC0>;
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timebase-frequency = <0x43B5FC0>;
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cpu@0 {
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phandle = <0x01>;
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device_type = "cpu";
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reg = <0x00>;
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status = "okay";
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compatible = "riscv";
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riscv,isa = "rv64imafdcsu";
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riscv,isa-extensions = "imafdc", "sstc", "svinval", "svnapot", "svpbmt", "zba", "zbb", "zbc", "zbs", "zicbom", "zicbop", "zicbopz", "zicntr", "zicsr", "zifencei", "zihpm";
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mmu-type = "riscv,sv48";
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interrupt-controller {
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#interrupt-cells = <0x01>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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phandle = <0x02>;
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};
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};
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};
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soc {
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#address-cells = <0x02>;
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#size-cells = <0x02>;
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compatible = "simple-bus";
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ranges;
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uart@10000000 {
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interrupts = <0x0a>;
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interrupt-parent = <0x03>;
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clock-frequency = <0x43B5FC0>;
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reg = <0x00 0x10000000 0x00 0x100>;
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compatible = "ns16550a";
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};
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plic@c000000 {
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phandle = <0x03>;
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riscv,ndev = <0x35>;
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reg = <0x00 0xc000000 0x00 0x210000>;
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interrupts-extended = <0x02 0x0b 0x02 0x09>;
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interrupt-controller;
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compatible = "sifive,plic-1.0.0\0riscv,plic0";
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#interrupt-cells = <0x01>;
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#address-cells = <0x00>;
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};
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mmc@13000 {
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interrupts = <0x14>;
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compatible = "riscv,axi-sd-card-1.0";
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reg = <0x00 0x13000 0x00 0x7F>;
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fifo-depth = <256>;
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bus-width = <4>;
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interrupt-parent = <0x03>;
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clock = <0x43B5FC0>;
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max-frequency = <0xF4240>;
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no-sdio;
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};
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clint@2000000 {
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interrupts-extended = <0x02 0x03 0x02 0x07>;
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reg = <0x00 0x2000000 0x00 0x10000>;
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compatible = "sifive,clint0\0riscv,clint0";
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};
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};
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};
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