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https://github.com/openhwgroup/cvw
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524 lines
22 KiB
Systemverilog
524 lines
22 KiB
Systemverilog
///////////////////////////////////////////
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// testbench-imperas.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified:
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//
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// Purpose: Wally Testbench and helper modules
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// Applies test programs from the Imperas suite
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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`include "wally-config.vh"
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module testbench();
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logic clk;
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logic reset;
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int test, i, errors, totalerrors;
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logic [31:0] sig32[0:10000];
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logic [`XLEN-1:0] signature[0:10000];
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logic [`XLEN-1:0] testadr;
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string InstrFName, InstrDName, InstrEName, InstrMName, InstrWName;
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logic [31:0] InstrW;
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logic [`XLEN-1:0] meminit;
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string tests64ic[] = '{
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"rv64ic/I-C-ADD-01", "3000",
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"rv64ic/I-C-ADDI-01", "3000",
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"rv64ic/I-C-ADDIW-01", "3000",
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"rv64ic/I-C-ADDW-01", "3000",
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"rv64ic/I-C-AND-01", "3000",
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"rv64ic/I-C-ANDI-01", "3000",
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"rv64ic/I-C-BEQZ-01", "3000",
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"rv64ic/I-C-BNEZ-01", "3000",
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"rv64ic/I-C-EBREAK-01", "2000",
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"rv64ic/I-C-J-01", "3000",
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"rv64ic/I-C-JALR-01", "4000",
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"rv64ic/I-C-JR-01", "4000",
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"rv64ic/I-C-LD-01", "3420",
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"rv64ic/I-C-LDSP-01", "3420",
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"rv64ic/I-C-LI-01", "3000",
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"rv64ic/I-C-LUI-01", "2000",
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"rv64ic/I-C-LW-01", "3110",
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"rv64ic/I-C-LWSP-01", "3110",
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"rv64ic/I-C-MV-01", "3000",
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"rv64ic/I-C-NOP-01", "2000",
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"rv64ic/I-C-OR-01", "3000",
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"rv64ic/I-C-SD-01", "3000",
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"rv64ic/I-C-SDSP-01", "3000",
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"rv64ic/I-C-SLLI-01", "3000",
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"rv64ic/I-C-SRAI-01", "3000",
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"rv64ic/I-C-SRLI-01", "3000",
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"rv64ic/I-C-SUB-01", "3000",
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"rv64ic/I-C-SUBW-01", "3000",
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"rv64ic/I-C-SW-01", "3000",
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"rv64ic/I-C-SWSP-01", "3000",
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"rv64ic/I-C-XOR-01", "3000"
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};
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string tests64iNOc[] = {
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"rv64i/I-MISALIGN_JMP-01","2000"
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};
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string tests64i[] = '{
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"rv64i/I-LW-01", "4110",
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"rv64i/I-ADD-01", "3000",
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"rv64i/I-ADDI-01", "3000",
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"rv64i/I-ADDIW-01", "3000",
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"rv64i/I-ADDW-01", "3000",
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"rv64i/I-AND-01", "3000",
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"rv64i/I-ANDI-01", "3000",
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"rv64i/I-AUIPC-01", "3000",
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"rv64i/I-BEQ-01", "4000",
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"rv64i/I-BGE-01", "4000",
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"rv64i/I-BGEU-01", "4000",
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"rv64i/I-BLT-01", "4000",
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"rv64i/I-BLTU-01", "4000",
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"rv64i/I-BNE-01", "4000",
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"rv64i/I-DELAY_SLOTS-01", "2000",
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"rv64i/I-EBREAK-01", "2000",
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"rv64i/I-ECALL-01", "2000",
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"rv64i/I-ENDIANESS-01", "2010",
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"rv64i/I-IO-01", "2050",
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"rv64i/I-JAL-01", "3000",
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"rv64i/I-JALR-01", "4000",
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"rv64i/I-LB-01", "4020",
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"rv64i/I-LBU-01", "4020",
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"rv64i/I-LD-01", "4420",
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"rv64i/I-LH-01", "4050",
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"rv64i/I-LHU-01", "4050",
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"rv64i/I-LUI-01", "2000",
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"rv64i/I-LW-01", "4110",
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"rv64i/I-LWU-01", "4110",
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"rv64i/I-MISALIGN_LDST-01", "2010",
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"rv64i/I-NOP-01", "2000",
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"rv64i/I-OR-01", "3000",
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"rv64i/I-ORI-01", "3000",
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"rv64i/I-RF_size-01", "2000",
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"rv64i/I-RF_width-01", "2000",
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"rv64i/I-RF_x0-01", "2010",
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"rv64i/I-SB-01", "4000",
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"rv64i/I-SD-01", "4000",
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"rv64i/I-SH-01", "4000",
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"rv64i/I-SLL-01", "3000",
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"rv64i/I-SLLI-01", "3000",
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"rv64i/I-SLLIW-01", "3000",
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"rv64i/I-SLLW-01", "3000",
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"rv64i/I-SLT-01", "3000",
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"rv64i/I-SLTI-01", "3000",
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"rv64i/I-SLTIU-01", "3000",
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"rv64i/I-SLTU-01", "3000",
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"rv64i/I-SRA-01", "3000",
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"rv64i/I-SRAI-01", "3000",
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"rv64i/I-SRAIW-01", "3000",
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"rv64i/I-SRAW-01", "3000",
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"rv64i/I-SRL-01", "3000",
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"rv64i/I-SRLI-01", "3000",
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"rv64i/I-SRLIW-01", "3000",
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"rv64i/I-SRLW-01", "3000",
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"rv64i/I-SUB-01", "3000",
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"rv64i/I-SUBW-01", "3000",
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"rv64i/I-SW-01", "4000",
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"rv64i/I-XOR-01", "3000",
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"rv64i/I-XORI-01", "3000",
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"rv64i/WALLY-ADD", "4000",
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"rv64i/WALLY-SUB", "4000",
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"rv64i/WALLY-ADDI", "3000",
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"rv64i/WALLY-ANDI", "3000",
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"rv64i/WALLY-ORI", "3000",
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"rv64i/WALLY-XORI", "3000",
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"rv64i/WALLY-SLTI", "3000",
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"rv64i/WALLY-SLTIU", "3000",
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"rv64i/WALLY-SLLI", "3000",
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"rv64i/WALLY-SRLI", "3000",
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"rv64i/WALLY-SRAI", "3000",
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"rv64i/WALLY-LOAD", "11bf0",
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"rv64i/WALLY-JAL", "4000",
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"rv64i/WALLY-STORE", "3000",
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"rv64i/WALLY-ADDIW", "3000",
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"rv64i/WALLY-SLLIW", "3000",
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"rv64i/WALLY-SRLIW", "3000",
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"rv64i/WALLY-SRAIW", "3000",
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"rv64i/WALLY-ADDW", "4000",
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"rv64i/WALLY-SUBW", "4000",
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"rv64i/WALLY-SLLW", "3000",
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"rv64i/WALLY-SRLW", "3000",
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"rv64i/WALLY-SRAW", "3000"
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};
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string tests32ic[] = '{
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// "rv32ic/WALLY-C-ADHOC-01", "2000",
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"rv32ic/I-C-ADD-01", "2000",
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"rv32ic/I-C-ADDI-01", "2000",
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"rv32ic/I-C-AND-01", "2000",
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"rv32ic/I-C-ANDI-01", "2000",
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"rv32ic/I-C-BEQZ-01", "2000",
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"rv32ic/I-C-BNEZ-01", "2000",
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"rv32ic/I-C-EBREAK-01", "2000",
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"rv32ic/I-C-J-01", "2000",
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"rv32ic/I-C-JALR-01", "3000",
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"rv32ic/I-C-JR-01", "3000",
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"rv32ic/I-C-LI-01", "2000",
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"rv32ic/I-C-LUI-01", "2000",
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"rv32ic/I-C-LW-01", "2110",
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"rv32ic/I-C-LWSP-01", "2110",
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"rv32ic/I-C-MV-01", "2000",
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"rv32ic/I-C-NOP-01", "2000",
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"rv32ic/I-C-OR-01", "2000",
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"rv32ic/I-C-SLLI-01", "2000",
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"rv32ic/I-C-SRAI-01", "2000",
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"rv32ic/I-C-SRLI-01", "2000",
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"rv32ic/I-C-SUB-01", "2000",
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"rv32ic/I-C-SW-01", "2000",
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"rv32ic/I-C-SWSP-01", "2000",
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"rv32ic/I-C-XOR-01", "2000"
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};
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string tests32iNOc[] = {
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"rv32i/I-MISALIGN_JMP-01","2000"
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};
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string tests32i[] = {
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"rv32i/I-ADD-01", "2000",
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"rv32i/I-ADDI-01","2000",
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"rv32i/I-AND-01","2000",
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"rv32i/I-ANDI-01","2000",
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"rv32i/I-AUIPC-01","2000",
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"rv32i/I-BEQ-01","3000",
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"rv32i/I-BGE-01","3000",
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"rv32i/I-BGEU-01","3000",
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"rv32i/I-BLT-01","3000",
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"rv32i/I-BLTU-01","3000",
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"rv32i/I-BNE-01","3000",
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"rv32i/I-DELAY_SLOTS-01","2000",
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"rv32i/I-EBREAK-01","2000",
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"rv32i/I-ECALL-01","2000",
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"rv32i/I-ENDIANESS-01","2010",
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"rv32i/I-IO-01","2030",
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"rv32i/I-JAL-01","3000",
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"rv32i/I-JALR-01","3000",
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"rv32i/I-LB-01","3020",
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"rv32i/I-LBU-01","3020",
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"rv32i/I-LH-01","3050",
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"rv32i/I-LHU-01","3050",
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"rv32i/I-LUI-01","2000",
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"rv32i/I-LW-01","3110",
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"rv32i/I-MISALIGN_LDST-01","2010",
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"rv32i/I-NOP-01","2000",
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"rv32i/I-OR-01","2000",
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"rv32i/I-ORI-01","2000",
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"rv32i/I-RF_size-01","2000",
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"rv32i/I-RF_width-01","2000",
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"rv32i/I-RF_x0-01","2010",
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"rv32i/I-SB-01","3000",
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"rv32i/I-SH-01","3000",
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"rv32i/I-SLL-01","2000",
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"rv32i/I-SLLI-01","2000",
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"rv32i/I-SLT-01","2000",
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"rv32i/I-SLTI-01","2000",
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"rv32i/I-SLTIU-01","2000",
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"rv32i/I-SLTU-01","2000",
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"rv32i/I-SRA-01","2000",
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"rv32i/I-SRAI-01","2000",
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"rv32i/I-SRL-01","2000",
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"rv32i/I-SRLI-01","2000",
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"rv32i/I-SUB-01","2000",
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"rv32i/I-SW-01","3000",
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"rv32i/I-XOR-01","2000",
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"rv32i/I-XORI-01","2000",
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"rv32i/WALLY-ADD", "3000",
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"rv32i/WALLY-SUB", "3000",
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"rv32i/WALLY-ADDI", "2000",
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"rv32i/WALLY-ANDI", "2000",
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"rv32i/WALLY-ORI", "2000",
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"rv32i/WALLY-XORI", "2000",
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"rv32i/WALLY-SLTI", "2000",
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"rv32i/WALLY-SLTIU", "2000",
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"rv32i/WALLY-SLLI", "2000",
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"rv32i/WALLY-SRLI", "2000",
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"rv32i/WALLY-SRAI", "2000",
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"rv32i/WALLY-LOAD", "11c00",
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"rv32i/WALLY-SUB", "3000",
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"rv32i/WALLY-STORE", "2000",
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"rv32i/WALLY-JAL", "3000"
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};
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string tests[];
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logic [`AHBW-1:0] HRDATAEXT;
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logic HREADYEXT, HRESPEXT;
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logic [31:0] HADDR;
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logic [`AHBW-1:0] HWDATA;
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logic HWRITE;
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logic [2:0] HSIZE;
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logic [2:0] HBURST;
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logic [3:0] HPROT;
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logic [1:0] HTRANS;
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logic HMASTLOCK;
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logic HCLK, HRESETn;
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// pick tests based on modes supported
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initial
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if (`XLEN == 64) begin // RV64
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tests = {tests64i};
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests64ic};
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else tests = {tests, tests64iNOc};
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end else begin // RV32
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tests = {tests32i};
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if (`C_SUPPORTED % 2 == 1) tests = {tests, tests32ic};
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else tests = {tests, tests32iNOc};
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end
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string signame, memfilename;
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logic [31:0] GPIOPinsIn, GPIOPinsOut, GPIOPinsEn;
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logic UARTSin, UARTSout;
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// instantiate device to be tested
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assign GPIOPinsIn = 0;
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assign UARTSin = 1;
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assign HREADYEXT = 1;
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assign HRESPEXT = 0;
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assign HRDATAEXT = 0;
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wallypipelinedsoc dut(.*);
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// Track names of instructions
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instrTrackerTB it(clk, reset, dut.hart.ieu.dp.FlushE,
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dut.hart.ifu.InstrD, dut.hart.ifu.InstrE,
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dut.hart.ifu.InstrM, InstrW,
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InstrDName, InstrEName, InstrMName, InstrWName);
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// initialize tests
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initial
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begin
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test = 0;
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totalerrors = 0;
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testadr = 0;
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// fill memory with defined values to reduce Xs in simulation
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if (`XLEN == 32) meminit = 32'hFEDC0123;
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else meminit = 64'hFEDCBA9876543210;
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for (i=0; i<=65535; i = i+1) begin
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//dut.imem.RAM[i] = meminit;
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// dut.uncore.RAM[i] = meminit;
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end
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// read test vectors into memory
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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reset = 1; # 22; reset = 0;
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end
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// generate clock to sequence tests
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always
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begin
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clk = 1; # 5; clk = 0; # 5;
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end
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// check results
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always @(negedge clk)
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begin
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if (dut.hart.priv.EcallFaultM &&
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(dut.hart.ieu.dp.regf.rf[3] == 1 || (dut.hart.ieu.dp.regf.we3 && dut.hart.ieu.dp.regf.a3 == 3 && dut.hart.ieu.dp.regf.wd3 == 1))) begin
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$display("Code ended with ecall with gp = 1");
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#60; // give time for instructions in pipeline to finish
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// clear signature to prevent contamination from previous tests
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for(i=0; i<10000; i=i+1) begin
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sig32[i] = 'bx;
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end
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// read signature, reformat in 64 bits if necessary
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signame = {"../../imperas-riscv-tests/work/", tests[test], ".signature.output"};
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$readmemh(signame, sig32);
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i = 0;
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while (i < 10000) begin
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if (`XLEN == 32) begin
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signature[i] = sig32[i];
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i = i+1;
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end else begin
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signature[i/2] = {sig32[i+1], sig32[i]};
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i = i + 2;
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end
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end
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// Check errors
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i = 0;
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errors = 0;
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if (`XLEN == 32)
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testadr = tests[test+1].atohex()/4;
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else
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testadr = tests[test+1].atohex()/8;
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/* verilator lint_off INFINITELOOP */
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while (signature[i] !== 'bx) begin
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//$display("signature[%h] = %h", i, signature[i]);
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if (signature[i] !== dut.uncore.dtim.RAM[testadr+i]) begin
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if (signature[i+4] !== 'bx || signature[i] !== 32'hFFFFFFFF) begin
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// report errors unless they are garbage at the end of the sim
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// kind of hacky test for garbage right now
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errors = errors+1;
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$display(" Error on test %s result %d: adr = %h sim = %h, signature = %h",
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tests[test], i, (testadr+i)*`XLEN/8, dut.uncore.dtim.RAM[testadr+i], signature[i]);
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end
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end
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i = i + 1;
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end
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/* verilator lint_on INFINITELOOP */
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if (errors == 0) $display("%s succeeded. Brilliant!!!", tests[test]);
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else begin
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$display("%s failed with %d errors. :(", tests[test], errors);
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totalerrors = totalerrors+1;
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end
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test = test + 2;
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if (test == tests.size()) begin
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if (totalerrors == 0) $display("SUCCESS! All tests ran without failures.");
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else $display("FAIL: %d test programs had errors", totalerrors);
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$stop;
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end
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else begin
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memfilename = {"../../imperas-riscv-tests/work/", tests[test], ".elf.memfile"};
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$readmemh(memfilename, dut.imem.RAM);
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$readmemh(memfilename, dut.uncore.dtim.RAM);
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$display("Read memfile %s", memfilename);
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reset = 1; # 17; reset = 0;
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end
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end
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end
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endmodule
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/* verilator lint_on STMTDLY */
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/* verilator lint_on WIDTH */
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module instrTrackerTB(
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input logic clk, reset, FlushE,
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input logic [31:0] InstrD,
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input logic [31:0] InstrE, InstrM,
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output logic [31:0] InstrW,
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output string InstrDName, InstrEName, InstrMName, InstrWName);
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// stage Instr to Writeback for visualization
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flopr #(32) InstrWReg(clk, reset, InstrM, InstrW);
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instrNameDecTB ddec(InstrD, InstrDName);
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instrNameDecTB edec(InstrE, InstrEName);
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instrNameDecTB mdec(InstrM, InstrMName);
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instrNameDecTB wdec(InstrW, InstrWName);
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endmodule
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// decode the instruction name, to help the test bench
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module instrNameDecTB(
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input logic [31:0] instr,
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output string name);
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logic [6:0] op;
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logic [2:0] funct3;
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logic [6:0] funct7;
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logic [11:0] imm;
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assign op = instr[6:0];
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assign funct3 = instr[14:12];
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assign funct7 = instr[31:25];
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assign imm = instr[31:20];
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// it would be nice to add the operands to the name
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// create another variable called decoded
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always_comb
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casez({op, funct3})
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10'b0000000_000: name = "BAD";
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10'b0000011_000: name = "LB";
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10'b0000011_001: name = "LH";
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10'b0000011_010: name = "LW";
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10'b0000011_011: name = "LD";
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10'b0000011_100: name = "LBU";
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10'b0000011_101: name = "LHU";
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10'b0000011_110: name = "LWU";
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10'b0010011_000: if (instr[31:15] == 0 && instr[11:7] ==0) name = "NOP/FLUSH";
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else name = "ADDI";
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10'b0010011_001: if (funct7[6:1] == 6'b000000) name = "SLLI";
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else name = "ILLEGAL";
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10'b0010011_010: name = "SLTI";
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10'b0010011_011: name = "SLTIU";
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10'b0010011_100: name = "XORI";
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10'b0010011_101: if (funct7[6:1] == 6'b000000) name = "SRLI";
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else if (funct7[6:1] == 6'b010000) name = "SRAI";
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else name = "ILLEGAL";
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10'b0010011_110: name = "ORI";
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10'b0010011_111: name = "ANDI";
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10'b0010111_???: name = "AUIPC";
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10'b0100011_000: name = "SB";
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10'b0100011_001: name = "SH";
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10'b0100011_010: name = "SW";
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10'b0100011_011: name = "SD";
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10'b0011011_000: name = "ADDIW";
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10'b0011011_001: name = "SLLIW";
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10'b0011011_101: if (funct7 == 7'b0000000) name = "SRLIW";
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else if (funct7 == 7'b0100000) name = "SRAIW";
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else name = "ILLEGAL";
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10'b0111011_000: if (funct7 == 7'b0000000) name = "ADDW";
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else if (funct7 == 7'b0100000) name = "SUBW";
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else name = "ILLEGAL";
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10'b0111011_001: name = "SLLW";
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10'b0111011_101: if (funct7 == 7'b0000000) name = "SRLW";
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else if (funct7 == 7'b0100000) name = "SRAW";
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else name = "ILLEGAL";
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10'b0110011_000: if (funct7 == 7'b0000000) name = "ADD";
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else if (funct7 == 7'b0000001) name = "MUL";
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else if (funct7 == 7'b0100000) name = "SUB";
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else name = "ILLEGAL";
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10'b0110011_001: if (funct7 == 7'b0000000) name = "SLL";
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else if (funct7 == 7'b0000001) name = "MULH";
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else name = "ILLEGAL";
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10'b0110011_010: if (funct7 == 7'b0000000) name = "SLT";
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else if (funct7 == 7'b0000001) name = "MULHSU";
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else name = "ILLEGAL";
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10'b0110011_011: if (funct7 == 7'b0000000) name = "SLTU";
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else if (funct7 == 7'b0000001) name = "DIV";
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else name = "ILLEGAL";
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10'b0110011_100: if (funct7 == 7'b0000000) name = "XOR";
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else if (funct7 == 7'b0000001) name = "MUL";
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else name = "ILLEGAL";
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10'b0110011_101: if (funct7 == 7'b0000000) name = "SRL";
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else if (funct7 == 7'b0000001) name = "DIVU";
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else if (funct7 == 7'b0100000) name = "SRA";
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else name = "ILLEGAL";
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10'b0110011_110: if (funct7 == 7'b0000000) name = "OR";
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else if (funct7 == 7'b0000001) name = "REM";
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else name = "ILLEGAL";
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10'b0110011_111: if (funct7 == 7'b0000000) name = "AND";
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else if (funct7 == 7'b0000001) name = "REMU";
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else name = "ILLEGAL";
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10'b0110111_???: name = "LUI";
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10'b1100011_000: name = "BEQ";
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10'b1100011_001: name = "BNE";
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10'b1100011_100: name = "BLT";
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10'b1100011_101: name = "BGE";
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10'b1100011_110: name = "BLTU";
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10'b1100011_111: name = "BGEU";
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10'b1100111_000: name = "JALR";
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10'b1101111_???: name = "JAL";
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10'b1110011_000: if (imm == 0) name = "ECALL";
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else if (imm == 1) name = "EBREAK";
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else if (imm == 2) name = "URET";
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else if (imm == 258) name = "SRET";
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else if (imm == 770) name = "MRET";
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else name = "ILLEGAL";
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10'b1110011_001: name = "CSRRW";
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10'b1110011_010: name = "CSRRS";
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10'b1110011_011: name = "CSRRC";
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10'b1110011_101: name = "CSRRWI";
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10'b1110011_110: name = "CSRRSI";
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10'b1110011_111: name = "CSRRCI";
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10'b0001111_???: name = "FENCE";
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default: name = "ILLEGAL";
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endcase
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endmodule
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