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76 lines
3.9 KiB
Systemverilog
76 lines
3.9 KiB
Systemverilog
///////////////////////////////////////////
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// fmaadd.sv
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//
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// Written: 6/23/2021 me@KatherineParry.com, David_Harris@hmc.edu
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// Modified:
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//
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// Purpose: FMA significand adder
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//
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// Documentation: RISC-V System on Chip Design Chapter 13 (Figure 13.11)
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fmaadd import cvw::*; #(parameter cvw_t P) (
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input logic [3*P.NF+3:0] Am, // aligned addend's mantissa for addition in U(NF+5.2NF+1)
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input logic [P.NE-1:0] Ze, // exponent of Z
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input logic Ps, // the product sign and the alligend addeded's sign (Modified Z sign for other opperations)
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input logic [P.NE+1:0] Pe, // product's exponet
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input logic [2*P.NF+1:0] Pm, // the product's mantissa
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input logic InvA, // invert the aligned addend
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input logic KillProd, // should the product be set to 0
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input logic ASticky, // Alighed addend's sticky bit
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output logic [3*P.NF+3:0] AmInv, // aligned addend possibly inverted
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output logic [2*P.NF+1:0] PmKilled, // the product's mantissa possibly killed
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output logic Ss, // sum's sign
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output logic [P.NE+1:0] Se, // sum's exponent
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output logic [3*P.NF+3:0] Sm // the positive sum
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);
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logic [3*P.NF+3:0] PreSum, NegPreSum; // possibly negitive sum
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logic NegSum; // was the sum negitive
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///////////////////////////////////////////////////////////////////////////////
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// Addition
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///////////////////////////////////////////////////////////////////////////////
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// Choose an inverted or non-inverted addend. Put carry into adder/LZA for addition
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assign AmInv = {3*P.NF+4{InvA}}^Am;
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// Kill the product if the product is too small to effect the addition (determined in fma1.sv)
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assign PmKilled = {2*P.NF+2{~KillProd}}&Pm;
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// Do the addition
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// - calculate a positive and negitive sum in parallel
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// if there was a small negitive number killed in the alignment stage one needs to be subtracted from the sum
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// prod - addend where some of the addend is put into the sticky bit then don't add +1 from negation
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// ie ~(InvA&ASticky&~KillProd)&InvA = (~ASticky|KillProd)&InvA
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// addend - prod where product is killed (and not exactly zero) then don't add +1 from negation
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// ie ~(InvA&ASticky&KillProd)&InvA = (~ASticky|~KillProd)&InvA
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// in this case this result is only ever selected when InvA=1 so we can remove &InvA
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assign {NegSum, PreSum} = {{P.NF+2{1'b0}}, PmKilled, 1'b0} + {InvA, AmInv} + {{3*P.NF+4{1'b0}}, (~ASticky|KillProd)&InvA};
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assign NegPreSum = Am + {{P.NF+1{1'b1}}, ~PmKilled, 1'b0} + {(3*P.NF+2)'(0), ~ASticky|~KillProd, 1'b0};
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// Choose the positive sum and accompanying LZA result.
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assign Sm = NegSum ? NegPreSum : PreSum;
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// is the result negitive
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// if p - z is the Sum negitive
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// if -p + z is the Sum positive
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// if -p - z then the Sum is negitive
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assign Ss = NegSum^Ps;
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assign Se = KillProd ? {2'b0, Ze} : Pe;
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endmodule
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