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3fc6bb0c40
Spent a long time trying to find a way to see if this condition was possible, only to become relativly convinced that it isn't. Basically, since RO cache writes only happen after a long period of stall for the bus access, there's no way a flushD can be active at the same time as a RO cache write. TrapM causes a FlushD, but interrupts are gated by the "commited" logic and the exception pipeline stalls. I feel like its worth keeping the logic to be safe so I've chosen to exclude it rather than explicitely remove it. |
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| .. | ||
| cache.sv | ||
| cachefsm.sv | ||
| cacheLRU.sv | ||
| cacheway.sv | ||
| subcachelineread.sv | ||