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Configurable RISC-V Processor
13 Commits 4 Branches 2 Tags 52 MiB
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Noah Boorstin 3f2820646d More testbench setup work 
- Copy bare-bones testbench from E85
   - have testbench instantiate a wallypipelinedhart so we can simulate memory/peripherals easier
 - Create .gitignore for vsim files
 - Make PC reset a macro, change to 0x1000 to conform to the bootloader

I don't know a good way to put the linux register trace file we're generating on git,
since its both nontrivial to make and way to big to keep in a git repo

for now it lives in /mnt/scratch/riscv_testbench/
2021-01-21 17:55:05 -05:00
riscv-o3@afb27bd558 Initial Checkin 2021-01-14 23:37:51 -05:00
wally-pipelined More testbench setup work 2021-01-21 17:55:05 -05:00
.gitignore More testbench setup work 2021-01-21 17:55:05 -05:00
LICENSE Initial Checkin 2021-01-14 23:37:51 -05:00
README.md Initial commit 2021-01-14 20:16:47 -08:00

README.md

riscv-wally

Configurable RISC-V Processor