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52 lines
2.0 KiB
Systemverilog
52 lines
2.0 KiB
Systemverilog
///////////////////////////////////////////
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// fdivsqrtfgen4.sv
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//
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// Written: David_Harris@hmc.edu, me@KatherineParry.com, cturek@hmc.edu
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// Modified:13 January 2022
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//
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// Purpose: Radix 4 F Addend Generator
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module fdivsqrtfgen4 import cvw::*; #(parameter cvw_t P) (
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input logic [3:0] udigit, // {2, 1, -1, -2}; all cold for zero
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input logic [P.DIVb+3:0] C, U, UM, // Q4.DIVb (extended from shorter forms)
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output logic [P.DIVb+3:0] F // Q4.DIVb
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);
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logic [P.DIVb+3:0] F2, F1, F0, FN1, FN2; // Q4.DIVb
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// Generate for both positive and negative digits
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assign F2 = (~U << 2) & (C << 2); //
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assign F1 = ~(U << 1) & C;
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assign F0 = 0;
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assign FN1 = (UM << 1) | (C & ~(C << 3));
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assign FN2 = (UM << 2) | ((C << 2) & ~(C << 4));
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// Choose which adder input will be used
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always_comb
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if (udigit[3]) F = F2;
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else if (udigit[2]) F = F1;
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else if (udigit[1]) F = FN1;
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else if (udigit[0]) F = FN2;
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else F = F0;
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endmodule
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