cvw/pipelined/src
2022-12-27 22:02:14 -08:00
..
cache Minor optimizations. 2022-12-23 20:11:36 -06:00
ebu Success we've replaced TrapM with FlushD in the IFU. 2022-12-22 21:36:49 -06:00
fpu Moved IDIV for postproc into generate block 2022-12-27 22:02:14 -08:00
generic Memory cleanup 2022-12-20 11:22:26 -08:00
hazard Minor optimizations. 2022-12-23 20:11:36 -06:00
ieu ALU cleanup 2022-12-24 07:18:35 -08:00
ifu Added about moving decompressed config generate. 2022-12-27 15:04:55 -06:00
lsu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
mdu Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
mmu Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. 2022-12-23 15:10:37 -06:00
ppa cleanup, plots for paper 2022-06-15 18:28:36 +00:00
privileged Fixed bug with the performance counters not updating. 2022-12-24 14:24:17 -06:00
uncore Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. 2022-12-21 09:00:09 -06:00
wally Renamed muldiv to mdu 2022-12-27 19:57:10 -08:00
sdc piplined directory cleanup 2022-01-07 12:43:50 +00:00