Ross Thompson 72be4318b8 Merge branch 'main' of https://github.com/openhwgroup/cvw into main		2023-02-26 12:06:06 -06:00
..
csr.sv	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
csrc.sv	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
csri.sv	Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.	2023-02-16 07:37:12 -08:00
csrm.sv	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
csrs.sv	Fixed missing assign when SSTC is not supported	2023-02-26 07:12:13 -08:00
csrsr.sv	Added SSTC support for supervisor timer compare, but presently disable support. Reenable for rv32gc and rv64gc after tests pass.	2023-02-16 07:37:12 -08:00
csru.sv	Merge branch 'main' of https://github.com/openhwgroup/cvw into dev	2023-02-03 08:36:11 -08:00
privdec.sv	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
privileged.sv	Renamed signals to match new figures.	2023-02-24 19:51:47 -06:00
privmode.sv	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00
privpiperegs.sv	Fixed Issue #106: fld rasies load access fault instead of illegal instruction. The IEU controller had considered all fp loads and stores to be legal regardless of whether the FPU is enabled or the type is supported. Merged illegal instruction detection from both units into the Decode stage, saving two bits of pipeline register as well.	2023-02-21 09:32:17 -08:00
trap.sv	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00