cvw/fpga/constraints
2024-10-30 16:01:11 -05:00
..
artyddr3.ucf
constraints-ArtyA7.xdc Fixed Arty constraints and corrected typos. 2024-08-30 14:17:37 -05:00
constraints-vcu108.xdc Modified fpga config to support two fpga boards with different amount of memory. 2024-08-29 16:12:58 -07:00
constraints-vcu118.xdc
debug2.xdc
debug4.xdc
debug6.xdc The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_all.txt The vcu108 works again. Added renumber.py script that renumbers probes in an xdc file. 2024-05-30 15:48:27 -05:00
marked_debug_rvvi.txt More updates to fpga IP module names. 2024-08-22 14:31:39 -07:00
marked_debug_small.txt
marked_debug_spi.txt Updates for arty A7 device tree. 2024-09-05 12:02:07 -07:00
marked_debug.txt The path to the zsbl was wrong all this time, but for reason was working with older versions of Ubuntu, but one 24.04 it causes vivado to not find the rom and ram. 2024-10-30 16:01:11 -05:00
small-debug-rvvi.xdc Updated for a better ILA rvvi debugger. 2024-07-22 17:44:04 -05:00
small-debug-spi.xdc The path to the zsbl was wrong all this time, but for reason was working with older versions of Ubuntu, but one 24.04 it causes vivado to not find the rom and ram. 2024-10-30 16:01:11 -05:00
small-debug.xdc Now have configurations to switch between supporting RVVI over ethernet. 2024-07-22 10:51:13 -05:00
vcu-small-debug.xdc VCU108 is not synthesizing at 50MHz. Still running into a few problems 2024-08-23 16:17:15 -07:00