mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
48 lines
1003 B
Makefile
48 lines
1003 B
Makefile
dst := IP
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sdc_src := ~/repos/sdc.tar.gz
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# vcu118
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#export XILINX_PART := xcvu9p-flga2104-2L-e
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#export XILINX_BOARD := xilinx.com:vcu118:part0:2.4
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#export board := vcu118
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# vcu108
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export XILINX_PART := xcvu095-ffva2104-2-e
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export XILINX_BOARD := xilinx.com:vcu108:part0:1.2
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export board := vcu108
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all: FPGA
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FPGA: PreProcessFiles IP SDC
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vivado -mode tcl -source wally.tcl 2>&1 | tee wally.log
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IP: $(dst)/xlnx_proc_sys_reset.log \
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$(dst)/xlnx_ddr4-$(board).log \
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$(dst)/xlnx_axi_clock_converter.log \
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$(dst)/xlnx_ahblite_axi_bridge.log
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SDC:
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cp $(sdc_src) ../src/
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tar xzf ../src/sdc.tar.gz -C ../src
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PreProcessFiles:
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rm -rf ../src/CopiedFiles_do_not_add_to_repo/
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cp -r ../../pipelined/src/ ../src/CopiedFiles_do_not_add_to_repo/
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./insert_debug_comment.sh
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$(dst)/%.log: %.tcl
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mkdir -p IP
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cd IP;\
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vivado -mode batch -source ../$*.tcl | tee $*.log
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cleanIP:
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rm -rf IP
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cleanLogs:
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rm -rf *.jou *.log
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cleanFPGA:
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rm -rf WallyFPGA.* reports sim .Xil
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cleanAll: cleanIP cleanLogs cleanFPGA
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