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32 lines
1.1 KiB
Systemverilog
Executable File
32 lines
1.1 KiB
Systemverilog
Executable File
//performs the fsgnj/fsgnjn/fsgnjx RISCV instructions
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module fpusgn (SgnOpCodeE, SgnResultE, SgnFlagsE, FInput1E, FInput2E);
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input [63:0] FInput1E, FInput2E;
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input [1:0] SgnOpCodeE;
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output [63:0] SgnResultE;
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output [4:0] SgnFlagsE;
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wire AonesExp;
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//op code designation:
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//
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//00 - fsgnj - directly copy over sign value of FInput2E
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//01 - fsgnjn - negate sign value of FInput2E
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//10 - fsgnjx - XOR sign values of FInput1E & FInput2E
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//
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assign SgnResultE[63] = SgnOpCodeE[1] ? (FInput1E[63] ^ FInput2E[63]) : (FInput2E[63] ^ SgnOpCodeE[0]);
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assign SgnResultE[62:0] = FInput1E[62:0];
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//If the exponent is all ones, then the value is either Inf or NaN,
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//both of which will produce a QNaN/SNaN value of some sort. This will
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//set the invalid flag high.
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assign AonesExp = FInput1E[62]&FInput1E[61]&FInput1E[60]&FInput1E[59]&FInput1E[58]&FInput1E[57]&FInput1E[56]&FInput1E[55]&FInput1E[54]&FInput1E[53]&FInput1E[52];
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//the only flag that can occur during this operation is invalid
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//due to changing sign on already existing NaN
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assign SgnFlagsE = {AonesExp & SgnResultE[63], 1'b0, 1'b0, 1'b0, 1'b0};
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endmodule
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