mirror of
https://github.com/openhwgroup/cvw
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b3aaa87cba
Since writing an SD card image generation script, the bootloader needed to be altered to access individual binaries from specific partitions. A new file, gpt.c with it's header gpt.h, have been added to the bootloader to facilitate this. The SDC has been added to the device tree for the VCU108 board. Additionally the SDC interrupt signal was added to the PLIC node in the device tree. The PLIC itself was modified to accept the SDC interrupt signal.
165 lines
4.5 KiB
Systemverilog
165 lines
4.5 KiB
Systemverilog
//////////////////////////////////////////
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// wally-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define FPGA 1
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`define QEMU 0
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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// IEEE 754 compliance
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`define IEEE754 0
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`define MISA (32'h0014112D)
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`define ZICSR_SUPPORTED 1
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`define ZIFENCEI_SUPPORTED 1
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`define ZICOUNTERS_SUPPORTED 1
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`define ZFH_SUPPORTED 0
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`define COUNTERS 32
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// LSU microarchitectural Features
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`define BUS_SUPPORTED 1
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`define DCACHE_SUPPORTED 1
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`define ICACHE_SUPPORTED 1
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`define VIRTMEM_SUPPORTED 1
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`define VECTORED_INTERRUPTS_SUPPORTED 1
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`define BIGENDIAN_SUPPORTED 1
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// TLB configuration. Entries should be a power of 2
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`define ITLB_ENTRIES 32
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`define DTLB_ENTRIES 32
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// Cache configuration. Sizes should be a power of two
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// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
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`define DCACHE_NUMWAYS 4
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`define DCACHE_WAYSIZEINBYTES 4096
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`define DCACHE_LINELENINBITS 512
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`define ICACHE_NUMWAYS 4
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`define ICACHE_WAYSIZEINBYTES 4096
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`define ICACHE_LINELENINBITS 512
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// Integer Divider Configuration
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// IDIV_BITSPERCYCLE must be 1, 2, or 4
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`define IDIV_BITSPERCYCLE 4
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`define IDIV_ON_FPU 1
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 64'h0000000000001000
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// WFI Timeout Wait
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`define WFI_TIMEOUT_BIT 16
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define DTIM_SUPPORTED 1'b0
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`define DTIM_BASE 56'h80000000
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`define DTIM_RANGE 56'h00001FFF
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`define IROM_SUPPORTED 1'b0
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`define IROM_BASE 56'h80000000
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`define IROM_RANGE 56'h00001FFF
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`define BOOTROM_SUPPORTED 1'b1
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`define BOOTROM_BASE 56'h00001000
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`define BOOTROM_RANGE 56'h00000FFF
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`define UNCORE_RAM_SUPPORTED 1'b1
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`define UNCORE_RAM_BASE 56'h000002000
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`define UNCORE_RAM_RANGE 56'h000000FFF
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`define EXT_MEM_SUPPORTED 1'b1
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`define EXT_MEM_BASE 56'h80000000
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`define EXT_MEM_RANGE 56'h07FFFFFF
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`define EXT_SUPPORTED 1'b0
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`define EXT_BASE 56'h80000000
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`define EXT_RANGE 56'h07FFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 56'h02000000
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`define CLINT_RANGE 56'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 56'h10060000
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`define GPIO_RANGE 56'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 56'h10000000
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`define UART_RANGE 56'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 56'h0C000000
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`define PLIC_RANGE 56'h03FFFFFF
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`define SDC_SUPPORTED 1'b0
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`define SDC_BASE 56'h00012100
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`define SDC_RANGE 56'h0000001F
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// Temporary Boot Process Stuff
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`define SDC2_SUPPORTED 1'b1
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`define SDC2_BASE 56'h00013000
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`define SDC2_RANGE 56'h0000007F
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// Bus Interface width
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`define AHBW 64
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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// Hardware configuration
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`define UART_PRESCALE 0
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// Interrupt configuration
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`define PLIC_NUM_SRC 53
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`define PLIC_UART_ID 10
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`define PLIC_GPIO_ID 3
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`define PLIC_SDC_ID 20
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`define BPRED_SUPPORTED 1
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`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
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`define BPRED_SIZE 10
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`define HPTW_WRITES_SUPPORTED 1
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// FPU division architecture
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`define RADIX 32'h4
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`define DIVCOPIES 32'h4
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// bit manipulation
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`define ZBA_SUPPORTED 0
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`define ZBB_SUPPORTED 0
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`define ZBC_SUPPORTED 0
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`define ZBS_SUPPORTED 0
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// Memory synthesis configuration
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`define USE_SRAM 0
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