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159 lines
9.9 KiB
Systemverilog
159 lines
9.9 KiB
Systemverilog
///////////////////////////////////////////
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// mmu.sv
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//
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// Written: david_harris@hmc.edu and kmacsaigoren@hmc.edu 4 June 2021
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// Modified:
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//
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// Purpose: Memory management unit, including TLB, PMA, PMP
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//
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// Documentation: RISC-V System on Chip Design
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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// https://github.com/openhwgroup/cvw
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module mmu import cvw::*; #(parameter cvw_t P,
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parameter TLB_ENTRIES = 8, IMMU = 0) (
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input logic clk, reset,
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input logic [P.XLEN-1:0] SATP_REGW, // Current value of satp CSR (from privileged unit)
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input logic STATUS_MXR, // Status CSR: make executable page readable
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input logic STATUS_SUM, // Status CSR: Supervisor access to user memory
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input logic STATUS_MPRV, // Status CSR: modify machine privilege
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input logic [1:0] STATUS_MPP, // Status CSR: previous machine privilege level
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input logic ENVCFG_PBMTE, // Page-based memory types enabled
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input logic ENVCFG_ADUE, // HPTW A/D Update enable
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input logic [1:0] PrivilegeModeW, // Current privilege level of the processeor
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input logic DisableTranslation, // virtual address translation disabled during D$ flush and HPTW walk that use physical addresses
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input logic [P.XLEN+1:0] VAdr, // virtual/physical address from IEU or physical address from HPTW
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input logic [1:0] Size, // access size: 00 = 8 bits, 01 = 16 bits, 10 = 32 bits , 11 = 64 bits
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input logic [P.XLEN-1:0] PTE, // page table entry
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input logic [1:0] PageTypeWriteVal, // page type
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input logic TLBWrite, // write TLB entry
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input logic TLBFlush, // Invalidate all TLB entries
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output logic [P.PA_BITS-1:0] PhysicalAddress, // PAdr when no translation, or translated VAdr (TLBPAdr) when there is translation
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output logic TLBMiss, // Miss TLB
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output logic Cacheable, // PMA indicates memory address is cachable
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output logic Idempotent, // PMA indicates memory address is idempotent
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output logic SelTIM, // Select a tightly integrated memory
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// Faults
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output logic InstrAccessFaultF, LoadAccessFaultM, StoreAmoAccessFaultM, // access fault sources
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output logic InstrPageFaultF, LoadPageFaultM, StoreAmoPageFaultM, // page fault sources
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output logic UpdateDA, // page fault due to setting dirty or access bit
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output logic LoadMisalignedFaultM, StoreAmoMisalignedFaultM, // misaligned fault sources
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// PMA checker signals
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input logic [3:0] CMOpM, // Cache management instructions
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input logic AtomicAccessM, ExecuteAccessF, WriteAccessM, ReadAccessM, // access type
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input var logic [7:0] PMPCFG_ARRAY_REGW[P.PMP_ENTRIES-1:0], // PMP configuration
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input var logic [P.PA_BITS-3:0] PMPADDR_ARRAY_REGW[P.PMP_ENTRIES-1:0] // PMP addresses
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);
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logic [P.PA_BITS-1:0] TLBPAdr; // physical address for TLB
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logic PMAInstrAccessFaultF; // Instruction access fault from PMA
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logic PMPInstrAccessFaultF; // Instruction access fault from PMP
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logic PMALoadAccessFaultM; // Load access fault from PMA
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logic PMPLoadAccessFaultM; // Load access fault from PMP
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logic PMAStoreAmoAccessFaultM; // Store or AMO access fault from PMA
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logic PMPStoreAmoAccessFaultM; // Store or AMO access fault from PMP
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logic DataMisalignedM; // load or store misaligned
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logic Translate; // Translation occurs when virtual memory is active and DisableTranslation is off
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logic TLBPageFault; // Page fault from TLB
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logic ReadNoAmoAccessM; // Read that is not part of atomic operation causes Load faults. Otherwise StoreAmo faults
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logic [1:0] PBMemoryType; // PBMT field of PTE during TLB hit, or 00 otherwise
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logic AmoMisalignedCausesAccessFaultM; // Misaligned AMO is not handled by hardware even with ZICCLSM, so it throws an access fault instead of misaligned with ZICCLSM
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logic AmoAccessM; // AMO access detected when ReadAccessM and WriteAccessM are simultaneously asserted
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// only instantiate TLB if Virtual Memory is supported
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if (P.VIRTMEM_SUPPORTED) begin:tlb
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logic ReadAccess, WriteAccess;
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assign ReadAccess = ExecuteAccessF | ReadAccessM; // execute also acts as a TLB read. Execute and Read are never active for the same MMU, so safe to mix pipestages
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assign WriteAccess = WriteAccessM;
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tlb #(.P(P), .TLB_ENTRIES(TLB_ENTRIES), .ITLB(IMMU)) tlb(
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.clk, .reset,
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.SATP_MODE(SATP_REGW[P.XLEN-1:P.XLEN-P.SVMODE_BITS]),
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.SATP_ASID(SATP_REGW[P.ASID_BASE+P.ASID_BITS-1:P.ASID_BASE]),
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.VAdr(VAdr[P.XLEN-1:0]), .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .ENVCFG_PBMTE, .ENVCFG_ADUE,
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.PrivilegeModeW, .ReadAccess, .WriteAccess, .CMOpM,
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.DisableTranslation, .PTE, .PageTypeWriteVal,
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.TLBWrite, .TLBFlush, .TLBPAdr, .TLBMiss,
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.Translate, .TLBPageFault, .UpdateDA, .PBMemoryType);
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end else begin:tlb // just pass address through as physical
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assign Translate = 1'b0;
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assign TLBMiss = 1'b0;
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assign TLBPageFault = 1'b0;
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assign PBMemoryType = 2'b00;
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assign UpdateDA = 1'b0;
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assign TLBPAdr = '0;
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end
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// If translation is occuring, select translated physical address from TLB
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// the lower 12 bits are the page offset. These are never changed from the orginal
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// non translated address.
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mux2 #(P.PA_BITS-12) addressmux(VAdr[P.PA_BITS-1:12], TLBPAdr[P.PA_BITS-1:12], Translate, PhysicalAddress[P.PA_BITS-1:12]);
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assign PhysicalAddress[11:0] = VAdr[11:0];
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///////////////////////////////////////////
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// Check physical memory accesses
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///////////////////////////////////////////
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pmachecker #(P) pmachecker(.PhysicalAddress, .Size, .CMOpM,
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.AtomicAccessM, .ExecuteAccessF, .WriteAccessM, .ReadAccessM, .PBMemoryType,
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.Cacheable, .Idempotent, .SelTIM,
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.PMAInstrAccessFaultF, .PMALoadAccessFaultM, .PMAStoreAmoAccessFaultM);
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if (P.PMP_ENTRIES > 0) begin : pmp
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pmpchecker #(P) pmpchecker(.PhysicalAddress, .PrivilegeModeW,
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.PMPCFG_ARRAY_REGW, .PMPADDR_ARRAY_REGW,
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.ExecuteAccessF, .WriteAccessM, .ReadAccessM, .CMOpM,
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.PMPInstrAccessFaultF, .PMPLoadAccessFaultM, .PMPStoreAmoAccessFaultM);
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end else begin
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assign PMPInstrAccessFaultF = 1'b0;
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assign PMPStoreAmoAccessFaultM = 1'b0;
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assign PMPLoadAccessFaultM = 1'b0;
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end
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assign ReadNoAmoAccessM = ReadAccessM & ~WriteAccessM;// AMO causes StoreAmo rather than Load fault
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assign AmoAccessM = ReadAccessM & WriteAccessM;
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// Misaligned faults
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always_comb // exclusion-tag: immu-wordaccess
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case(Size[1:0])
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2'b00: DataMisalignedM = 1'b0; // lb, sb, lbu
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2'b01: DataMisalignedM = VAdr[0]; // lh, sh, lhu
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2'b10: DataMisalignedM = VAdr[1] | VAdr[0]; // lw, sw, flw, fsw, lwu
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2'b11: DataMisalignedM = |VAdr[2:0]; // ld, sd, fld, fsd
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endcase
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// When ZiCCLSM_SUPPORTED, misalgined cachable loads and stores are handled in hardware so they do not throw a misaligned fault
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assign LoadMisalignedFaultM = DataMisalignedM & ReadNoAmoAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss;
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assign StoreAmoMisalignedFaultM = DataMisalignedM & WriteAccessM & ~(P.ZICCLSM_SUPPORTED & Cacheable) & ~TLBMiss; // Store and AMO both assert WriteAccess
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// Access faults
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// If TLB miss and translating we want to not have faults from the PMA and PMP checkers.
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assign InstrAccessFaultF = (PMAInstrAccessFaultF | PMPInstrAccessFaultF) & ~TLBMiss;
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assign LoadAccessFaultM = (PMALoadAccessFaultM | PMPLoadAccessFaultM) & ~TLBMiss;
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// a misaligned AMO causes an access fault rather than a misaligned fault if a misaligned load/store is handled in hardware
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// this is subtle - see privileged spec 3.6.3.3
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// AMO is detected as ReadAccess & WriteAccess
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assign AmoMisalignedCausesAccessFaultM = DataMisalignedM & AmoAccessM & (P.ZICCLSM_SUPPORTED & Cacheable);
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assign StoreAmoAccessFaultM = (PMAStoreAmoAccessFaultM | PMPStoreAmoAccessFaultM | AmoMisalignedCausesAccessFaultM) & ~TLBMiss;
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// Specify which type of page fault is occurring
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assign InstrPageFaultF = TLBPageFault & ExecuteAccessF;
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assign LoadPageFaultM = TLBPageFault & ReadNoAmoAccessM;
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assign StoreAmoPageFaultM = TLBPageFault & (WriteAccessM | (|CMOpM));
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endmodule
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