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https://github.com/openhwgroup/cvw
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281 lines
11 KiB
Systemverilog
281 lines
11 KiB
Systemverilog
///////////////////////////////////////////
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// loggers.sv
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//
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// Written: Ross Thompson ross1728@gmail.com
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// Modified: 14 June 2023
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//
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// Purpose: Log branch instructions, log instruction fetches,
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// log I$ misses, log data memory accesses, log D$ misses, and
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// log other related operations
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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module loggers import cvw::*; #(parameter cvw_t P,
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parameter PrintHPMCounters,
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parameter I_CACHE_ADDR_LOGGER,
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parameter D_CACHE_ADDR_LOGGER,
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parameter BPRED_LOGGER) (
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input logic clk,
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input logic reset,
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input logic DCacheFlushStart,
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input logic DCacheFlushDone,
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// input logic BeginSample,
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// input logic StartSample,
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// input logic EndSample,
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input string memfilename,
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input string TEST
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);
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// performance counter logging
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logic BeginSample;
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logic StartSample, EndSample;
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if((PrintHPMCounters | BPRED_LOGGER) & P.ZICNTR_SUPPORTED) begin : HPMCSample
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integer HPMCindex;
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logic StartSampleFirst;
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logic StartSampleDelayed, BeginDelayed;
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logic EndSampleFirst, EndSampleDelayed;
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logic [P.XLEN-1:0] InitialHPMCOUNTERH[P.COUNTERS-1:0];
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string HPMCnames[] = '{"Mcycle",
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"------",
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"InstRet",
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"Br Count",
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"Jump Not Return",
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"Return",
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"BP Wrong",
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"BP Dir Wrong",
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"BP Target Wrong",
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"RAS Wrong",
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"Instr Class Wrong",
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"Load Stall",
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"Store Stall",
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"D Cache Access",
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"D Cache Miss",
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"D Cache Cycles",
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"I Cache Access",
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"I Cache Miss",
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"I Cache Cycles",
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"CSR Write",
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"FenceI",
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"SFenceVMA",
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"Interrupt",
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"Exception",
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"Divide Cycles"
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};
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always_comb
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if (TEST == "embench") begin
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StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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end else if (TEST == "coremark") begin
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StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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end else begin
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StartSampleFirst = reset;
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EndSample = DCacheFlushStart & ~DCacheFlushDone;
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end
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/*
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if(TEST == "embench") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_trigger";
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_trigger";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else if(TEST == "coremark") begin
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// embench runs warmup then runs start_trigger
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// embench end with stop_trigger.
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//assign StartSampleFirst = FunctionName.FunctionName.FunctionName == "start_time";
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign EndSampleFirst = FunctionName.FunctionName.FunctionName == "stop_time";
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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end else begin
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// default start condiction is reset
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// default end condiction is end of test (DCacheFlushDone)
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//assign StartSampleFirst = reset;
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//flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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//assign StartSample = StartSampleFirst & ~ StartSampleDelayed;
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//assign EndSample = DCacheFlushStart & ~DCacheFlushDone;
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flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed);
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assign BeginSample = StartSampleFirst & ~BeginDelayed;
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end
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*/
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flopr #(1) StartSampleReg(clk, reset, StartSampleFirst, StartSampleDelayed);
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assign StartSample = StartSampleFirst & ~StartSampleDelayed;
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flopr #(1) EndSampleReg(clk, reset, EndSampleFirst, EndSampleDelayed);
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assign EndSample = EndSampleFirst & ~ EndSampleDelayed;
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flop #(1) BeginReg(clk, StartSampleFirst, BeginDelayed); // ** is this redundant with StartSampleReg?
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assign BeginSample = StartSampleFirst & ~BeginDelayed;
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always @(negedge clk) begin
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if(StartSample) begin
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for(HPMCindex = 0; HPMCindex < 32; HPMCindex += 1) begin
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InitialHPMCOUNTERH[HPMCindex] <= dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex];
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end
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end
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if(EndSample) begin
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for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
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// unlikely to have more than 10M in any counter.
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$display("Cnt[%2d] = %7d %s", HPMCindex, dut.core.priv.priv.csr.counters.counters.HPMCOUNTER_REGW[HPMCindex] - InitialHPMCOUNTERH[HPMCindex], HPMCnames[HPMCindex]);
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end
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end
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end
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end
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if (P.ICACHE_SUPPORTED && I_CACHE_ADDR_LOGGER) begin : ICacheLogger
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int file;
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string LogFile;
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logic resetD, resetEdge;
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logic Enable;
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logic InvalDelayed, InvalEdge;
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assign Enable = dut.core.ifu.bus.icache.icache.cachefsm.LRUWriteEn &
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dut.core.ifu.immu.immu.pmachecker.Cacheable &
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~dut.core.ifu.bus.icache.icache.cachefsm.FlushStage &
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dut.core.ifu.bus.icache.icache.cachefsm.CacheEn &
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~reset;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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flop #(1) InvalReg(clk, dut.core.ifu.InvalidateICacheM, InvalDelayed);
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assign InvalEdge = dut.core.ifu.InvalidateICacheM & ~InvalDelayed;
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initial begin
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LogFile = "ICache.log";
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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string AccessTypeString, HitMissString;
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always @(*) begin
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HitMissString = dut.core.ifu.bus.icache.icache.Hit ? "H" :
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dut.core.ifu.bus.icache.icache.vict.cacheLRU.AllValid ? "E" : "M";
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(Enable) begin // only log i cache reads
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$fwrite(file, "%h R %s\n", dut.core.ifu.PCPF, HitMissString);
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end
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if(InvalEdge) $fwrite(file, "0 I X\n");
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (P.DCACHE_SUPPORTED && D_CACHE_ADDR_LOGGER) begin : DCacheLogger
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int file;
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string LogFile;
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logic resetD, resetEdge;
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logic Enabled;
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string AccessTypeString, HitMissString;
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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always @(*) begin
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HitMissString = dut.core.lsu.bus.dcache.dcache.Hit ? "H" :
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(!dut.core.lsu.bus.dcache.dcache.vict.cacheLRU.AllValid) ? "M" :
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dut.core.lsu.bus.dcache.dcache.LineDirty ? "D" : "E";
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AccessTypeString = dut.core.lsu.bus.dcache.FlushDCache ? "F" :
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dut.core.lsu.LSUAtomicM[1] ? "A" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b10 ? "R" :
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dut.core.lsu.bus.dcache.CacheRWM == 2'b01 ? "W" :
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"NULL";
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end
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assign Enabled = dut.core.lsu.bus.dcache.dcache.cachefsm.LRUWriteEn &
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~dut.core.lsu.bus.dcache.dcache.cachefsm.FlushStage &
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dut.core.lsu.dmmu.dmmu.pmachecker.Cacheable &
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dut.core.lsu.bus.dcache.dcache.cachefsm.CacheEn &
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(AccessTypeString != "NULL");
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initial begin
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LogFile = "DCache.log";
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file = $fopen(LogFile, "w");
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$fwrite(file, "BEGIN %s\n", memfilename);
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end
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always @(posedge clk) begin
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if(resetEdge) $fwrite(file, "TRAIN\n");
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if(BeginSample) $fwrite(file, "BEGIN %s\n", memfilename);
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if(Enabled) begin
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$fwrite(file, "%h %s %s\n", dut.core.lsu.PAdrM, AccessTypeString, HitMissString);
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end
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if(dut.core.lsu.bus.dcache.dcache.cachefsm.FlushFlag) $fwrite(file, "0 F X\n");
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if(EndSample) $fwrite(file, "END %s\n", memfilename);
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end
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end
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if (P.BPRED_SUPPORTED) begin : BranchLogger
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if (BPRED_LOGGER) begin
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string direction;
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int file, CFIfile;
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logic PCSrcM;
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string LogFile, CFILogFile;
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logic resetD, resetEdge;
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flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.PCSrcE, PCSrcM);
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flop #(1) ResetDReg(clk, reset, resetD);
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assign resetEdge = ~reset & resetD;
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initial begin
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LogFile = "branch.log"; // will break some of Ross's research analysis scripts
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CFILogFile = "cfi.log"; // will break some of Ross's research analysis scripts
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//LogFile = $psprintf("branch_%s%0d.log", P.BPRED_TYPE, P.BPRED_SIZE);
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file = $fopen(LogFile, "w");
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CFIfile = $fopen(CFILogFile, "w");
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end
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always @(posedge clk) begin
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if(resetEdge) begin
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$fwrite(file, "TRAIN\n");
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$fwrite(CFIfile, "TRAIN\n");
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end
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if(StartSample) begin
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$fwrite(file, "BEGIN %s\n", memfilename);
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$fwrite(CFIfile, "BEGIN %s\n", memfilename);
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end
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if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(file, "%h %s\n", dut.core.PCM, direction);
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end
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if((|dut.core.ifu.InstrClassM) & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
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direction = PCSrcM ? "t" : "n";
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$fwrite(CFIfile, "%h %s\n", dut.core.PCM, direction);
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end
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if(EndSample) begin
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$fwrite(file, "END %s\n", memfilename);
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$fwrite(CFIfile, "END %s\n", memfilename);
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end
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end
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end
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end
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endmodule
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