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https://github.com/openhwgroup/cvw
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109 lines
3.9 KiB
Systemverilog
109 lines
3.9 KiB
Systemverilog
//////////////////////////////////////////
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// busybear-config.vh
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//
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// Written: David_Harris@hmc.edu 4 January 2021
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// Modified:
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//
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// Purpose: Specify which features are configured
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// Macros to determine which modes are supported based on MISA
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//
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// A component of the Wally configurable RISC-V project.
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//
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// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
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//
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// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
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// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
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// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
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// is furnished to do so, subject to the following conditions:
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//
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// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
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//
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// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
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// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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///////////////////////////////////////////
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// include shared configuration
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`include "wally-shared.vh"
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`define BUILDROOT 0
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`define BUSYBEAR 1
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`define LINUX_FIX_READ {'h10000005}
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`define LINUX_TEST_VECTORS "/courses/e190ax/busybear_boot/"
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// RV32 or RV64: XLEN = 32 or 64
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`define XLEN 64
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`define MISA (32'h0014112D)
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`define ZCSR_SUPPORTED 1
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`define ZCOUNTERS_SUPPORTED 1
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`define COUNTERS 32
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// Microarchitectural Features
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`define UARCH_PIPELINED 1
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`define UARCH_SUPERSCALR 0
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`define UARCH_SINGLECYCLE 0
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`define MEM_DCACHE 0
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`define MEM_DTIM 1
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`define MEM_ICACHE 0
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`define MEM_VIRTMEM 0
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`define VECTORED_INTERRUPTS_SUPPORTED 1 // Domenico Ottolia 4/15: Support for vectored interrupts in _tvec csrs. Just implemented in src/privileged/trap.sv around line 75. Pretty sure this should be 1.
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`define ITLB_ENTRY_BITS 5
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`define DTLB_ENTRY_BITS 5
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// Legal number of PMP entries are 0, 16, or 64
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`define PMP_ENTRIES 16
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// Address space
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`define RESET_VECTOR 64'h0000000000001000
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// Peripheral Addresses
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// Peripheral memory space extends from BASE to BASE+RANGE
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// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
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`define BOOTTIM_SUPPORTED 1'b1
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`define BOOTTIM_BASE 32'h00000000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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`define BOOTTIM_RANGE 32'h00003FFF
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//`define BOOTTIM_BASE 32'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
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//`define BOOTTIM_RANGE 32'h00000FFF
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`define TIM_SUPPORTED 1'b1
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`define TIM_BASE 32'h80000000
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`define TIM_RANGE 32'h07FFFFFF
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`define CLINT_SUPPORTED 1'b1
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`define CLINT_BASE 32'h02000000
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`define CLINT_RANGE 32'h0000FFFF
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`define GPIO_SUPPORTED 1'b1
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`define GPIO_BASE 32'h10012000
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`define GPIO_RANGE 32'h000000FF
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`define UART_SUPPORTED 1'b1
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`define UART_BASE 32'h10000000
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`define UART_RANGE 32'h00000007
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`define PLIC_SUPPORTED 1'b1
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`define PLIC_BASE 32'h0C000000
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`define PLIC_RANGE 32'h03FFFFFF
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// Bus Interface width
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`define AHBW 64
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// Test modes
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// Tie GPIO outputs back to inputs
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`define GPIO_LOOPBACK_TEST 0
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// Hardware configuration
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//`define UART_PRESCALE 1
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`define UART_PRESCALE 0
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// Interrupt configuration
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`define PLIC_NUM_SRC 53
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`define PLIC_UART_ID 4
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`define TWO_BIT_PRELOAD "../config/busybear/twoBitPredictor.txt"
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`define BTB_PRELOAD "../config/busybear/BTBPredictor.txt"
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`define BPTYPE "BPGSHARE" // BPGLOBAL or BPTWOBIT or BPGSHARE
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`define BPRED_ENABLED 1
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