mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
27 lines
1002 B
Tcl
27 lines
1002 B
Tcl
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#set partNumber $::env(XILINX_PART)
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#set boardNmae $::env(XILINX_BOARD)
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set partNumber xcvu9p-flga2104-2L-e
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set boardName xilinx.com:vcu118:part0:2.4
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set ipName xlnx_axi_clock_converter
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create_project $ipName . -force -part $partNumber
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set_property board_part $boardName [current_project]
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create_ip -name axi_clock_converter -vendor xilinx.com -library ip -module_name $ipName
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set_property -dict [list CONFIG.ACLK_ASYNC {1} \
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CONFIG.PROTOCOL {AXI4} \
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CONFIG.ADDR_WIDTH {32} \
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CONFIG.DATA_WIDTH {64} \
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CONFIG.ID_WIDTH {4} \
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CONFIG.MI_CLK.FREQ_HZ {208333333} \
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CONFIG.SI_CLK.FREQ_HZ {10000000}] [get_ips $ipName]
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generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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generate_target all [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
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launch_run -jobs 8 ${ipName}_synth_1
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wait_on_run ${ipName}_synth_1
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