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57 lines
1.9 KiB
Systemverilog
57 lines
1.9 KiB
Systemverilog
///////////////////////////////////////////
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// fregfile.sv
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//
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// Written: David_Harris@hmc.edu 9 January 2021
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// Modified: James Stine
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//
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// Purpose: 3R1W 4-port register file for FPU
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//
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// Documentation: RISC-V System on Chip Design Chapter 13
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//
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// A component of the CORE-V-WALLY configurable RISC-V project.
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//
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// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
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//
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// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
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//
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// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
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// except in compliance with the License, or, at your option, the Apache License version 2.0. You
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// may obtain a copy of the License at
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//
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// https://solderpad.org/licenses/SHL-2.1/
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//
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// Unless required by applicable law or agreed to in writing, any work distributed under the
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// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
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// either express or implied. See the License for the specific language governing permissions
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// and limitations under the License.
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////////////////////////////////////////////////////////////////////////////////////////////////
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`include "wally-config.vh"
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module fregfile (
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input logic clk, reset,
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input logic we4, // write enable
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input logic [4:0] a1, a2, a3, a4, // adresses
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input logic [`FLEN-1:0] wd4, // write data
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output logic [`FLEN-1:0] rd1, rd2, rd3 // read data
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);
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logic [`FLEN-1:0] rf[31:0];
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integer i;
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// three ported register file
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// read three ports combinationally (A1/RD1, A2/RD2, A3/RD3)
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// write fourth port on rising edge of clock (A4/WD4/WE4)
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// write occurs on falling edge of clock
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always_ff @(negedge clk) // or posedge reset)
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if (reset) for(i=0; i<32; i++) rf[i] <= 0;
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else if (we4) rf[a4] <= wd4;
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assign #2 rd1 = rf[a1];
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assign #2 rd2 = rf[a2];
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assign #2 rd3 = rf[a3];
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endmodule // regfile
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